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www.gennum.com GS9090 genlinx? iii 270mb/s deserializer for sdi and dvb-asi GS9090 data sheet 28201 - 1 july 2005 1 of 70 key features ? smpte 259m-c compliant descrambling and nrzi to nrz decoding (with bypass) ? dvb-asi sync word detection and 8b/10b decoding ? integrated line-based fifo for data alignment/delay, clock phase interchange, dvb-asi data packet extraction and clock rate interchange, and ancillary data packet extraction ? integrated vco and reclocker ? automatic or manual selection between smpte video and dvb-asi data ? single serial digital input buffer with wide input sensitivity ? user selectable additional processing features including: ? trs, anc data checksum, and edh crc error detection and correction ? programmable anc data detection ? illegal code remapping ? internal flywheel for noise immune h, v, f extraction ? automatic standards detection and indication ? enhanced gennum serial peripheral interface (gspi) ? jtag test interface ? polarity insensitive for dvb-asi and smpte signals ? +1.8v core power supply with optional +1.8v or +3.3v i/o power supply ? small footprint (8mm x 8mm) ? low power operation (typically 145mw) ? pb-free and rohs compliant applications ? smpte 259m-c serial digital interfaces ? dvb-asi serial digital interfaces description the GS9090 is a 270mb/s reclocking deserializer with an internal fifo. when used in conjunction with one of gennum?s sdi cable equalizers, a receive solution for sd-sdi and dvb-asi applications can be realized. in addition to reclocking and deserializing the input data stream, the GS9090 performs nrzi-to-nrz decoding, descrambling as per smpte 259m-c, and word alignment when operating in smpte mode. when operating in dvb-asi mode, the device will word align the data to k28.5 sync characters and 8b/10b decode the received stream. the integrated reclocker features a very wide input jitter tolerance, and is fully compatible with both smpte and dvb-asi input streams. the GS9090 includes a range of data processing functions such as error detection and correction, automatic standards detection, and edh support. the device can also detect and extract smpte 352m payload identifier packets and independently identify the received video standard. this information is read from internal registers via the host interface port. trs errors, edh crc erro rs, and ancillary data checksum errors can all be detected and corrected. a single data_error pin is provided which is an inverted logical 'or'ing of all detectable errors. individual error status is stored in internal ?error_status? registers. the GS9090 also incorporates a video line-based fifo. this fifo may be used in four user-selectable modes to carry out tasks such as data alignment / delay, clock phase interchange, mpeg packet extraction and clock rate interchange, and ancillary data packet extraction. parallel data outputs are prov ided in 10-bit multiplexed format, with the associated parallel clock output signal operating at 27mhz. the GS9090 is pb-free, and the encapsulation compound does not contain halogenated flame retardant (rohs compliant).
GS9090 data sheet 28201 - 1 july 2005 2 of 70 GS9090 functional block diagram ddi_1 term ddi_1 reclocker s->p smpte de- scramble, word alignment and flywheel dout[9:0] carrier_detect reset asi sync detect host interface / jtag test cs_tms sclk_tc k sdin_tdi sdout_tdo data_error jtag/ho st trs check csum check anc data detection k28.5 sync detect, dvb-asi word alignment and 8b/10b decode trs correct csum correct edh check & correct illegal code re- map dvb_asi pll_lock lf+ lb_cont pclk locked lock detect smpte_b ypass smpte sync dete ct lf- auto/m an programmable i/o stat[3:0] fifo fw_en ioproc_en rd_clk rd_reset
GS9090 data sheet 28201 - 1 july 2005 3 of 70 contents key features.................................................................................................................1 applications................................................................................................................... 1 description .................................................................................................................... 1 1. pin out .................................................................................................................... .5 1.1 pin assignment ...............................................................................................5 1.2 pin descriptions ..............................................................................................6 2. electrical characteristics ........................................................................................12 2.1 absolute maximum rating s ..........................................................................12 2.2 dc electrical characteristics ............. ...........................................................12 2.3 ac electrical characteristics........... ..............................................................13 2.4 solder reflow profiles...................................................................................16 2.5 host interface map........................................................................................17 2.5.1 host interface map (r/w registers) ....................................................18 2.5.2 host interface map (read only re gisters) ......... .............. ........... .........19 3. detailed description ...............................................................................................20 3.1 functional overview .....................................................................................20 3.2 serial digital input .........................................................................................21 3.3 clock and data recovery . .............. .............. .............. .............. ........... .........21 3.3.1 internal vco and phase detector ......................................................21 3.4 serial-to-parallel conversion ............ ...........................................................21 3.5 modes of operation......................................................................................22 3.5.1 lock detect.........................................................................................22 3.5.2 auto mode ..........................................................................................24 3.5.3 manual mode ......................................................................................25 3.6 smpte functionality ....................................................................................25 3.6.1 smpte descrambling and word alignment .......................................26 3.6.2 internal flywheel........................ .........................................................26 3.6.3 switch line lock handling..................................................................27 3.6.4 hvf timing signal generation ..... ......................................................28 3.7 dvb-asi functionality ..................................................................................29 3.7.1 dvb-asi 8b/10b decoding .............. .............. .............. .............. .........29 3.7.2 status signal outputs .........................................................................29 3.8 data-through functionalit y.............. .............. .............. .............. ........... .........29 3.9 additional processing features ......... ...........................................................30 3.9.1 fifo load pulse..... .............. .............. .............. .............. ........... .........30 3.9.2 ancillary data detection and indi cation ..............................................31 3.9.3 edh packet detection .................. ......................................................33 3.9.4 edh flag detection ............................................................................33 3.9.5 smpte 352m payload identifier.........................................................36 3.9.6 automatic video standard and data format detection ......................37
GS9090 data sheet 28201 - 1 july 2005 4 of 70 3.9.7 error detection and indication ... .........................................................38 3.9.8 error correction and insertion ............................................................43 3.10 internal fifo operation ..............................................................................46 3.10.1 video mode.......................................................................................46 3.10.2 dvb-asi mode .................................................................................48 3.10.3 ancillary data extraction mode... .............. .............. .............. ............51 3.10.4 bypass mode ....................................................................................54 3.11 parallel data outputs....................... ...........................................................55 3.11.1 parallel data bus ..................... .........................................................55 3.11.2 parallel output in smpte mode .......................................................56 3.11.3 parallel output in dvb-asi mode .....................................................56 3.11.4 parallel output in data-through mode .............................................56 3.12 programmable multi-function outputs .......................................................56 3.13 GS9090 low-latency mode.........................................................................58 3.14 gspi host interface ....................................................................................59 3.14.1 command word description.......... .............. .............. .............. .........60 3.14.2 data read and write timing ............................................................60 3.14.3 configuration and status registers ..................................................62 3.15 reset operation..........................................................................................63 3.16 jtag operation ..........................................................................................63 3.17 device power up ........................................................................................64 4. references & relevant standards ........... .............. .............. .............. ........... .........65 5. application information.... .......................................................................................66 5.1 typical application circuit (part a) ...............................................................66 5.2 typical application circuit (part b) ...............................................................67 6. package & ordering informa tion............................................................................68 6.1 package dimensions ....................................................................................68 6.2 recommended pcb footprint ................ .............. .............. .............. ............69 6.3 packaging data.............................................................................................69 6.4 ordering information .....................................................................................69 7. revision history .....................................................................................................70
GS9090 data sheet 28201 - 1 july 2005 5 of 70 1. pin out 1.1 pin assignment figure 1-1: pin assignment sdout_tdo io_gnd rd_reset ioproc_en nc term jtag/host ddi buff_vdd pll_vdd pll_gnd lf- ddi core_vdd cs_tms vco_gnd io_vdd dout2 dout3 dout4 dout5 dout6 dout7 dout8 dout9 dvb_asi pclk locked core_gnd smpte_bypass auto/man fifo_en lb_cont lf+ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 stat0 sclk_tck io_vdd reset rd_clk io_vdd buff_gnd vbg nc dout1 dout0 core_gnd sdin_tdi data_error stat1 stat2 stat3 io_gnd io_gnd vco_vdd fw_en core_vdd center pad (bottom of package) GS9090 xxxxe3 yyww gennum
GS9090 data sheet 28201 - 1 july 2005 6 of 70 1.2 pin descriptions table 1-1: pin descriptions pin number name timing type description 1 lf- analog input loop filter component connecti on. connect to pin 56 (lf+) as shown in the typical application circuit (part b) on page 67 . 2 pll_gnd analog input power ground connection for phase-locked loop. connect to gnd. 3 pll_vdd analog input power power supply connection for phase-locked loop. connect to +1.8v dc. 4 buff_vdd analog input power power supply connection fo r digital input buffers. when operating with 1.8v input as r equired by the current silicon this pin should be left unconnected. when operating with 3.3v input (avail able in future silicon) this pin should be connected to +3.3v as shown in the typical application circuit (part b) on page 67 . 5, 6 ddi, ddi analog input serial digital differential input pair. 7 buff_gnd analog input power ground connection for serial digi tal input buffer. connect to gnd. 8 term analog input termination for serial digital input. ac couple to buff_gnd 9, 11 nc ? ? no connect. 10 vbg analog input bandgap filter capacitor. connect to gnd as shown in the typical application circuit (part b) on page 67 . 12 ioproc_en non synchronous input control signal input signal levels are lvcmos / lvttl compatible. used to enable or disable the i/o processing features. when set high, the following i/o proc essing features of the device are enabled: ? illegal code remapping ? edh crc error correction ? ancillary data checksum error correction ? trs error correction ? edh flag detection to enable a subset of these feat ures, keep the ioproc_en pin high and disable the individual feature(s) in the ioproc_disable register accessible via the host interface. when set low, the device will enter low-latency mode. note: when the internal fifo is configured for video mode or ancillary data extraction mode, the ioproc_en pin must be set high (see internal fifo operation on page 46 ).
GS9090 data sheet 28201 - 1 july 2005 7 of 70 13 jtag/host non synchronous input control signal input signal levels are lvcmos / lvttl compatible. used to select jtag test mode or host interface mode. when set high, cs _tms, sclk_tck, sdout_tdo, and sdin_tdi are configured for jtag boundary scan testing. when set low, cs _tms, sclk_tck, sdout_tdo, and sdin_tdi are configured as gspi pins fo r normal host interface operation. 14 reset non synchronous input control signal input signal levels are lvcmos / lvttl compatible. used to reset the internal operating conditions to default setting or to reset the jtag test sequence. host mode (jtag/host = low): when asserted low, all functional blocks will be set to default conditions and all output signals become high impedance with the exception of the stat pins and the data_error pin which will maintain the last state they were in for the duration that reset is asserted. jtag test mode (jtag/host = high): when asserted low, all functional bl ocks will be set to default and the jtag test sequence will be held in reset. when set high, normal operation of the jtag test sequence resumes. note: see device power up on page 64 for power on reset requirements. 15, 45 core_vdd non synchronous input power power supply for digital logic blocks. connect to +1.8v dc. note: for power sequencing requirements, see device power up on page 64 . 16 cs _tms synchronous with sclk_tck input control signal input signal levels are lvcmos / lvttl compatible. chip select / test mode select host mode (jtag/host = low): cs _tms operates as the host interface chip select, cs , and is active low. jtag test mode (jtag/host = high): cs _tms operates as the jtag test mode select, tms, and is active high. 17 sclk_tck non synchronous input control signal input signal levels are lvcmos / lvttl compatible. serial data clock / test clock. all jtag / host interface address and data are shifted into/out of the dev ice synchronously with this clock. host mode (jtag/host = low): sclk_tck operates as the host interface serial data clock, sclk. jtag test mode (jtag/host = high): sclk_tck operates as the jtag test clock, tck. 18, 48 core_gnd non synchronous input power ground connection for digital logic blocks. connect to gnd. table 1-1: pin descriptions (continued) pin number name timing type description
GS9090 data sheet 28201 - 1 july 2005 8 of 70 19 sdout_tdo synchronous with sclk_tck output control signal input signal levels are lvcmos / lvttl compatible. serial data output / test data output host mode (jtag/host = low): sdout_tdo operates as the host interface serial output, sdout, used to read status and configuration information from the internal registers of the device. jtag test mode (jtag/host = high): sdout_tdo operates as the jtag test data output, tdo. 20 sdin_tdi synchronous with sclk_tck input control signal input signal levels are lvcmos / lvttl compatible. serial data input / test data input host mode (jtag/host = low): sdin_tdi operates as the host inte rface serial input, sdin, used to write address and configuration information to the internal registers of the device. jtag test mode (jtag/host = high): sdin_tdi operates as the jtag test data input, tdi. 21, 29, 43 io_vdd non synchronous input power power supply for digital i/o. for a 3.3v tolerant i/o, connect pins to either +1.8v dc or +3.3v dc. for a 5v tolerant i/o, connect pins to a +3.3v dc. note: for power sequencing requirements, see device power up on page 64 . 22 data_error synchronous with pclk output status signal output. signal levels are lvcmos / lvttl compatible. the data_error signal will be low when an error within the received data stream has been detected by the device. this pin is an inverted logical ?or?ing of all detectable errors listed in the internal error_status register. once an error is detected, data_error will remain low until the start of the next video frame / field, or until the error_status register is read via the host interface. the data_error signal will be high when the received data stream has been detected without error. note: it is possible to program wh ich error conditions are monitored by the device by setting appropriate bits in the error_mask register high. all error conditions are detected by default. table 1-1: pin descriptions (continued) pin number name timing type description
GS9090 data sheet 28201 - 1 july 2005 9 of 70 23, 25, 26, 27 stat[0:3] synchronous with pclk or rd_clk output multi function i/o port signal levels are lvcmos / lvttl compatible. programmable multi-function outputs. by programming the bits is the io_config register, each pin can output one of the following signals: ?h ?v ?f ? fifo_ld ? anc_detect ? edh_detect ?fifo_full ?fifo_empty these pins are set to certain default values depending on the configuration of the device and the internal fifo mode selected. see programmable multi-function outputs on page 56 for details. 24, 28, 42 io_gnd non synchronous input power ground connection for digital i/o. connect to gnd. 30 rd_clk ? input fifo read clock signal levels are lvcmos / lvttl compatible. the application layer cloc ks the parallel data out of the fifo on the rising edge of rd_clk. 31 rd_reset synchronous with rd_clk input fifo read reset signal levels are lvcmos / lvttl compatible. valid input only when the device is in smpte mode (smpte_bypass = high and dvb-asi = low), and the in ternal fifo is configured for video mode (see video mode on page 46 ). a high to low transition will reset t he fifo pointer to address zero of the memory. 32 - 41 dout[0:9] synchronous with rd_clk or pclk output parallel video data bus signal levels are lvcmos / lvttl compatible. when the internal fifo is enabled and configured for either video mode or dvb-asi mode, parallel data will be clocked out of the device on the rising edge of rd_clk. when the internal fifo is in bypass mode, parallel data will be clocked out of the device on the rising edge of pclk. dout9 is the msb and dout0 is the lsb. 44 pclk ? output pixel clock output signal levels are lvcmos / lvttl compatible. 27mhz parallel clock output. table 1-1: pin descriptions (continued) pin number name timing type description
GS9090 data sheet 28201 - 1 july 2005 10 of 70 46 locked synchronous with pclk output status signal output signal levels are lvcmos / lvttl compatible. the locked signal will be high whenever the device has correctly received and locked to smpte compliant data in smpte mode or dvb-asi compliant data in dvb-asi mode, or when the reclocker has achieved lock in data-through mode. it will be low otherwise. when t he signal is low, all digital output signals will be forced to logic low levels. 47 dvb_asi non synchronous input / output control signal input / status signal output signal levels are lvcmos / lvttl compatible. this pin is an input set by the appl ication layer in manual mode, and an output set by the device in auto mode. auto mode (auto/man = high): the dvb_asi signal will be high onl y when the device has locked to a dvb-asi compliant data stream. it will be low otherwise. manual mode (auto/man = low): when the application layer sets th is pin high, the device will be configured to operate in dvb-asi mode. the smpte_bypass pin will be ignored. when set low, the device will not support the decoding or word alignment of received dvb-asi data. 49 smpte_bypass non synchronous input / output control signal input / status signal output signal levels are lvcmos / lvttl compatible. this pin is an input set by the appl ication layer in manual mode, and an output set by the device in auto mode. auto mode (auto/man = high): the smpte_bypass signal will be high only when the device has locked to a smpte compliant data stream. it will be low otherwise. when the signal is low, no i/o pr ocessing features are available. manual mode (auto/man = low): when the application layer sets this pin high in conjunction with dvb_asi = low, the device will be configured to operate in smpte mode. all i/o processing features may be enabled in this mode. when the smpte_bypass pin is set low, the device will not support the descrambling, decoding, or wo rd alignment of received smpte data. no i/o processing fe atures will be available. 50 auto/man non synchronous input control signal input signal levels are lvcmos / lvttl compatible. when set high, the GS9090 will operate in auto mode. the dvb_asi and smpte_bypass pins become output status signals set by the device. in this mode, the GS9090 wi ll automatically de tect, reclock, deserialize, and process smpte or dvb-asi compliant input data. when set low, the GS9090 will operate in manual mode. the dvb_asi and smpte_bypass pins become input control signals. in this mode, the application layer must set these two external pins for the correct reception of either smpte or dvb-asi data. manual mode also supports the reclocking and deseriali zing of data not conforming to smpte or dvb-asi streams. table 1-1: pin descriptions (continued) pin number name timing type description
GS9090 data sheet 28201 - 1 july 2005 11 of 70 51 fw_en non synchronous input contol signal input signal levels are lvcmos / lvttl compatible. used to enable or disable the noi se immune flywheel of the device. when set high, the internal flywheel is enabled. this flywheel is used in the extraction of timing signals, the generation of trs signals, the automatic detection of video standards, and in manual switch line lock handling. when set low, the internal flyw heel is disabled. timing based trs errors will not be detected. 52 fifo_en non synchronous input contol signal input signal levels are lvcmos / lvttl compatible. used to enable / disable the internal fifo. when fifo_en is high, the internal fi fo will be enabled. data will be clocked out of the device on the rising edge of the rd_clk input pin if the fifo is in video mode or dvb-asi mode. when fifo_en is low, the internal fifo is bypassed and parallel data is clocked out on the rising edge of the pclk output. 53 vco_vdd analog input power power supply connection for voltage-co ntrolled-oscillator. connect to +1.8v dc. 54 lb_cont analog input control signal input control voltage to fine-tune the loop bandwidth of the pll. 55 vco_gnd analog input power ground connection for voltage-contro lled-oscillator. connect to gnd. 56 lf+ analog input loop filter component connection. connect to pin 1 (lf-) as shown in the typical application circuit (part b) on page 67 . ? center pad ? power connect to gnd following the recommended pcb footprint on page 69 table 1-1: pin descriptions (continued) pin number name timing type description
GS9090 data sheet 28201 - 1 july 2005 12 of 70 2. electrical characteristics 2.1 absolute maximum ratings 2.2 dc electrical characteristics table 2-1: absolute maximum ratings parameter value/units supply voltage core -0.3v to +2.1v supply voltage i/o -0.3v to +3.47v input voltage range (any input) -2.0v to + 5.25v ambient operating temperature -20c < t a < 85c storage temperature -40c < t stg < 125c esd protection on all pins (see note 2) 1kv notes: 1. see reflow solder profile 2. hbm, per jesda - 114b table 2-2: dc electrical characteristics v dd = 1.8v, t a = 0c to 70c, unless otherwise specified. parameter symbol condition min typ max units notes system operating temperature range t a ? 0 25 70 c 1 core power supply voltage core_vdd ? 1.71 1.8 1.89 v ? digital i/o buffer power supply voltage io_vdd 1.8v operation 1.71 1.8 1.89 v ? io_vdd 3.3v operation 3.13 3.3 3.47 v ? pll power supply voltage pll_vdd ? 1.71 1.8 1.89 v ? vco power supply voltage vco_vdd ? 1.71 1.8 1.89 v ? typical system power p d core_vdd = 1.8v io_vdd = 1.8v t = 25 o c ? 145 ? mw ? max. system power p d core_vdd = 1.89v io_vdd = 3.47v t = 70 o c ? ? 200 mw ?
GS9090 data sheet 28201 - 1 july 2005 13 of 70 2.3 ac electrical characteristics digital i/o input voltage, logic low v il 1.8v operation or 3.3v operation ? ? 0.35 x io_vdd v? input voltage, logic high v ih 1.8v operation or 3.3v operation 0.65 x io_vdd ??v? output voltage, logic low v ol i ol = 8ma @ 3.3v, 4ma @ 1.8v ??0.4v? output voltage, logic high v oh i ol = -8ma @ 3.3v, -4ma @ 1.8v io_vdd - 0.4 ??v? serial digital input input termination resistance r in ? 37.55062.5 ? notes: 1. all dc and ac electrical para meters within specification. table 2-2: dc electrical characteristics (continued) v dd = 1.8v, t a = 0c to 70c, unless otherwise specified. parameter symbol condition min typ max units notes table 2-3: ac electrical characteristics v dd = 1.8v, t a = 0c to 70c, unless otherwise specified. parameter symbol condition min typ max units notes system asynchronous lock time (locked signal set high) t lock input jitter of 0.2ui, no data to smpte, smpte_bypass = high dvb_asi = low, at 25c ??235us1 asynchronous lock time (locked signal set high) t lock input jitter of 0.2ui, no data to dvb-asi, smpte_bypass = high dvb_asi = high, at 25c ??185us1 asynchronous lock time (locked signal set high) t lock input jitter of 0.2ui, no data to non-smpte, smpte_bypass = low dvb_asi = low, at 25c ??165us1
GS9090 data sheet 28201 - 1 july 2005 14 of 70 serial digital input serial input data rate dr sdi ? ? 270 ? mb/s ? serial input jitter tolerance ijt ? ? 0.4 ? ui 2 serial digital input signal swing v ddi differential with internal 100 input termination 400 800 1700 mv p-p 3 parallel output parallel output clock frequency f pclk ??27?mhz? parallel output clock duty cycle dc pclk ?40?60%? variation of parallel output clock (from 27mhz) ? device unlocked t a = -20c to +85c io_vdd = 1.8v -7.5 ? +7.5 % 4 output data hold time t oh with 15pf load 3.0 ? ? ns 5 output delay time t od with 15pf load ? ? 10.0 ns 5 gspi gspi input clock frequency f gspi ? ? ? 54.0 mhz ? gspi clock duty cycle dc gspi ?40?60%? gspi setup time t gs ?1.5??ns? gspi hold time t gh ???1.5ns? notes: 1. no signal to signal present, or a switch from another data rate to 270mb/s. 2. power supply noise 50mv pp at 15khz, 100khz, 1mhz sinusoidal modulation. 3. see figure 2-1 . 4. when the serial input to the GS9090 is removed, the pclk out put signal will continue to operat e at 27mhz and the internal vco will remain at this frequency within +/- 7.5% over the range -20 o c to +85 o c. 5. timing includes the following outputs: dout[9:0], stat[3:0]. when the fifo is enabled, the outputs are measured with respect to rd_clk. table 2-3: ac electrical characteristics (continued) v dd = 1.8v, t a = 0c to 70c, unless otherwise specified. parameter symbol condition min typ max units notes
GS9090 data sheet 28201 - 1 july 2005 15 of 70 figure 2-1: serial digita l input signal swing v ddi v ddi 2 v ddi 2 v ddi 2 + 0 v ddi 2 _ v ddi 2 v dd _ v ddi 2 v dd _ v dd v dd single-ended swing (ddi) single-ended swing (ddi) differential swing (ddi-ddi)
GS9090 data sheet 28201 - 1 july 2005 16 of 70 2.4 solder reflow profiles the device is manufactured with matte-sn te rminations and is compatible with both standard eutectic and pb-free solder re flow profiles. msl qualification was performed using the maximum pb-free reflow profile shown in figure 2-2 . the recommended standard eutectic reflow profile is shown in figure 2-3 . figure 2-2: maximum pb-free solder reflow profile (preferred) figure 2-3: standard eutectic solder reflow profile (pb-free package) 25?c 150?c 200?c 217?c 260?c 250?c time temperature 8 min. max 60-180 sec. max 60-150 sec. 20-40 sec. 3?c/sec max 6?c/sec max 25?c 100?c 150?c 183?c 230?c 220?c time temperature 6 min. max 120 sec. max 60-150 sec. 10-20 sec. 3?c/sec max 6?c/sec max
28201 - 1 july 2005 17 of 70 GS9090 data sheet 2.5 host interface map table 2-4: host interface map register name address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 fifo_ld_position[12:0] 28h not used not used not usedb12b11b10b9b8b7b6b5b4b3b2b1b0 27h 26h error_mask_register 25h not used not used not used not used not used not used not used not used not used vd_std_ err_ mask ff_crc_ err_ mask ap_crc_ err_ mask lock_ err_ mask ccs_err_m ask sav_err_ma sk eav_err_ma sk ff_pixel_end_f1[12:0] 24h not used not used not usedb12b11b10b9b8b7b6b5b4b3b2b1b0 ff_pixel_start_f1[12:0] 23h not used not used not usedb12b11b10b9b8b7b6b5b4b3b2b1b0 ff_pixel_end_f0[12:0] 22h not used not used not usedb12b11b10b9b8b7b6b5b4b3b2b1b0 ff_pixel_start_f0[12:0] 21h not used not used not usedb12b11b10b9b8b7b6b5b4b3b2b1b0 ap_pixel_end_f1[12:0] 20h not used not used not usedb12b11b10b9b8b7b6b5b4b3b2b1b0 ap_pixel_start_f1[12:0] 1fh not used not used not usedb12b11b10b9b8b7b6b5b4b3b2b1b0 ap_pixel_end_f0[12:0] 1eh not used not used not usedb12b11b10b9b8b7b6b5b4b3b2b1b0 ap_pixel_start_f0[12:0] 1dh not used not used not usedb12b11b10b9b8b7b6b5b4b3b2b1b0 ff_line_end_f1[10:0] 1ch not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 ff_line_start_f1[10:0] 1bh not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 ff_line_end_f0[10:0] 1ah not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 ff_line_start_f0[10:0] 19h not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 ap_line_end_f1[10:0] 18h not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 ap_line_start_f1[10:0] 17h not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 ap_line_end_f0[10:0] 16h not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 ap_line_start_f0[10:0] 15h not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 raster_structure4[10:0] 14h not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 raster_structure3[12:0] 13h not used not used not usedb12b11b10b9b8b7b6b5b4b3b2b1b0 raster_structure2[12:0] 12h not used not used not usedb12b11b10b9b8b7b6b5b4b3b2b1b0 raster_structure1[10:0] 11h not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 video_format_out_b(4,3) 10h vfo4-b7 vfo4-b6 vfo4-b5 vfo4-b4 vfo4-b3 vfo4-b2 vfo4-b1 vfo4-b0 vfo3-b7 vfo3-b6 vfo3-b5 vfo3-b4 vfo3-b3 vfo3-b2 vfo 3-b1 vfo3-b0 video_format_out_a(2,1) 0fh vfo2-b7 vfo2-b6 vfo2-b5 vfo2-b4 vfo2-b3 vfo2-b2 vfo2-b1 vfo2-b0 vfo1-b7 vfo1-b6 vfo1-b5 vfo1-b4 vfo1-b3 vfo1-b2 vfo 1-b1 vfo1-b0 anc_type(5)[15:0] 0ehb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0 anc_type(4)[15:0] 0dhb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0 anc_type(3)[15:0] 0chb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0 anc_type(2)[15:0] 0bhb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0 anc_type(1)[15:0] 0ahb15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0 anc_line_b[10:0] 09h not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 anc_line_a[10:0] 08h not used not used not used not used not usedb10b9b8b7b6b5b4b3b2b1b0 fifo_full_offset 07h not used not used not used not used not used not used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 fifo_empty_offset 06h not used not used not used not used not used not used b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 io_config 05h not used not used not used anc_ data_ switch stat3_ config b2 stat3_ config b1 stat3_ config b0 stat2_ config b2 stat2_ config b1 stat2_ config b0 stat1_ config b2 stat1_ config b1 stat1_ config b0 stat0_ config b2 stat0_ config b1 stat0_ config b0 data_format 04h not used not used not used not used edh_ flag_ update ap_crc_v ff_crc_v edh_ detect version_35 2m not used not used std_ lock data_ format b3 data_ format b2 data_ format b1 data_ format b0 edh_flag_out 03h not used anc-ues anc-ida anc-idh anc-eda a nc-edh ff-ues ff-ida ff-idh ff-eda ff-edh ap-ues ap-ida ap-idh ap-eda ap-edh edh_flag_in 02h not used anc-ues_in anc-ida_in anc-idh_in anc- eda_in anc-edh_in ff-ues_in ff-ida_in ff-idh_in ff-eda_in ff-edh_in ap-ues_in ap-ida_in ap-idh _in ap-eda_in ap-edh_in error_status 01h not used not used not used not used not used not used not used not used not used vd_std_ err ff_crc_ err ap_crc_ err lock_ err ccs_err sav_err eav_err ioproc_disable 00h not used not used not used not used not used not used anc_pkt_ex t fifo_ mode b1 fifo_ mode b0 h_ config not used not used illegal_re map edh_crc_in s anc_ csum_ ins trs_in note: addresses 02ch to 42bh store the contents of the internal fifo. the contents may be accessed in ancillary data extraction mode (see section 3.10.3 ).
28201 - 1 july 2005 18 of 70 GS9090 data sheet 2.5.1 host interface map (r/w registers) table 2-5: host interface map (r/w registers) register name address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 fifo_ld_position[12:0] 28h b12b11b10b9b8b7b6b5b4b3b2b1b0 27h 26h error_mask_register 25h vd_std_ err_ mask ff_crc_ err_ mask ap_crc_ err_ mask lock_ err_ mask ccs_err_m ask sav_err_ma sk eav_err_ma sk ff_pixel_end_f1[12:0] 24h b12b11b10b9b8b7b6b5b4b3b2b1b0 ff_pixel_start_f1[12:0] 23h b12b11b10b9b8b7b6b5b4b3b2b1b0 ff_pixel_end_f0[12:0] 22h b12b11b10b9b8b7b6b5b4b3b2b1b0 ff_pixel_start_f0[12:0] 21h b12b11b10b9b8b7b6b5b4b3b2b1b0 ap_pixel_end_f1[12:0] 20h b12b11b10b9b8b7b6b5b4b3b2b1b0 ap_pixel_start_f1[12:0] 1fh b12b11b10b9b8b7b6b5b4b3b2b1b0 ap_pixel_end_f0[12:0] 1eh b12b11b10b9b8b7b6b5b4b3b2b1b0 ap_pixel_start_f0[12:0] 1dh b12b11b10b9b8b7b6b5b4b3b2b1b0 ff_line_end_f1[10:0] 1ch b10b9b8b7b6b5b4b3b2b1b0 ff_line_start_f1[10:0] 1bh b10b9b8b7b6b5b4b3b2b1b0 ff_line_end_f0[10:0] 1ah b10b9b8b7b6b5b4b3b2b1b0 ff_line_start_f0[10:0] 19h b10b9b8b7b6b5b4b3b2b1b0 ap_line_end_f1[10:0] 18h b10b9b8b7b6b5b4b3b2b1b0 ap_line_start_f1[10:0] 17h b10b9b8b7b6b5b4b3b2b1b0 ap_line_end_f0[10:0] 16h b10b9b8b7b6b5b4b3b2b1b0 ap_line_start_f0[10:0] 15h b10b9b8b7b6b5b4b3b2b1b0 14h 13h 12h 11h 10h 0fh anc_type(5)[15:0] 0eh b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 anc_type(4)[15:0] 0dh b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 anc_type(3)[15:0] 0ch b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 anc_type(2)[15:0] 0bh b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 anc_type(1)[15:0] 0ah b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 anc_line_b[10:0] 09h b10b9b8b7b6b5b4b3b2b1b0 anc_line_a[10:0] 08h b10b9b8b7b6b5b4b3b2b1b0 fifo_full_offset 07h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 fifo_empty_offset 06h b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 io_config 05h anc_ data_ switch stat3_ config b2 stat3_ config b1 stat3_ config b0 stat2_ config b2 stat2_ config b1 stat2_ config b0 stat1_ config b2 stat1_ config b1 stat1_ config b0 stat0_ config b2 stat0_ config b1 stat0_ config b0 data_format 04h edh_ flag_ update 03h 02h 01h ioproc_disable 00h anc_pkt_ex t fifo_ mode b1 fifo_ mode b0 h_ config illegal_re map edh_crc_in s anc_ csum_ ins trs_in note: addresses 02ch to 42bh store the contents of the internal fifo. the contents may be accessed in ancillary data extraction mode (see section 3.10.3 ).
28201 - 1 july 2005 19 of 70 GS9090 data sheet 2.5.2 host interface map (r ead only registers) table 2-6: host interface map (read only registers) register name address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 28h 27h 26h 25h 24h 23h 22h 21h 20h 1fh 1eh 1dh 1ch 1bh 1ah 19h 18h 17h 16h 15h raster_structure4[10:0] 14h b10b9b8b7b6b5b4b3b2b1b0 raster_structure3[12:0] 13h b12b11b10b9b8b7b6b5b4b3b2b1b0 raster_structure2[12:0] 12h b12b11b10b9b8b7b6b5b4b3b2b1b0 raster_structure1[10:0] 11h b10b9b8b7b6b5b4b3b2b1b0 video_format_out_b(4,3) 10h vfo4-b7 vfo4-b6 vfo4-b5 vfo4-b4 vfo4-b3 vfo4-b2 vfo4-b1 vfo4-b0 vfo3-b7 vfo3-b6 vfo3-b5 vfo3-b4 vfo3-b3 vfo3-b2 vfo 3-b1 vfo3-b0 video_format_out_a(2,1) 0fh vfo2-b7 vfo2-b6 vfo2-b5 vfo2-b4 vfo2-b3 vfo2-b2 vfo2-b1 vfo2-b0 vfo1-b7 vfo1-b6 vfo1-b5 vfo1-b4 vfo1-b3 vfo1-b2 vfo 1-b1 vfo1-b0 0eh 0dh 0ch 0bh 0ah 09h 08h 07h 06h 05h data_format 04h ap_crc_v ff_crc_v edh_ detect version_35 2m std_ lock data_ format b3 data_ format b2 data_ format b1 data_ format b0 edh_flag_out 03h not used anc-ues anc-ida anc-idh anc-eda anc-edh ff-ues ff-ida ff-idh ff-eda ff-edh ap-ues ap-ida ap-idh ap-eda ap-edh edh_flag_in 02h not used anc-ues _in anc-ida _in anc-idh _in anc-eda _in anc-edh _in ff-ues_in ff-ida_in ff-idh_in ff-eda_in ff-edh_in ap-ues_in ap-ida_in ap-idh_in ap-eda_in ap-edh_in error_status 01h vd_std_ err ff_crc_ err ap_crc_ err lock_ err ccs_err sav_err eav_err 00h note: addresses 02ch to 42bh store the contents of the internal fifo. the contents may be accessed in ancillary data extraction mode (see section 3.10.3 ).
GS9090 data sheet 28201 - 1 july 2005 20 of 70 3. detailed description ? functional overview on page 20 ? serial digital input on page 21 ? clock and data recovery on page 21 ? serial-to-parallel conversion on page 21 ? modes of operation on page 22 ? smpte functionality on page 25 ? dvb-asi functionality on page 29 ? data-through functionality on page 29 ? additional processing features on page 30 ? internal fifo operation on page 46 ? parallel data outputs on page 55 ? programmable multi-function outputs on page 56 ? GS9090 low-latency mode on page 58 ? gspi host interface on page 59 ? jtag operation on page 63 ? device power up on page 64 3.1 functional overview the GS9090 is a 270mb/s reclocking des erializer with an internal fifo and programmable multi-function output port . the device has two basic modes of operation which determine precisely how smpte or dvb-asi co mpliant input data streams are reclocked and processed. in auto mode (auto/man = high), the GS9090 will auto matically detect, reclock, deserialize, and process sd smpt e 259m-c, or dvb-asi input data. in manual mode (auto/man = low), the application layer must set external device pins for the correct reception of either smpte or dvb-asi data. manual mode also supports the reclocking and deserializing of 270mb/s data not conforming to smpte or dvb-asi streams. the digital signal processing core implements several data processing functions including error detection and correction and automatic video standards detection. these features are all enabled by default , but may be individually disabled via internal registers accessible through the gspi host interface. the provided programmable multi-function outp ut pins may be configured to output various status signals includi ng h, v, and f timing, anc illary data detection, edh detection, and a fifo load pulse. th e internal fifo supports 4 modes of operation, which may be used for data alignment / delay, mpeg packet extraction, or ancillary data extraction. the GS9090 contains a jtag interface for boundary scan test implementations.
GS9090 data sheet 28201 - 1 july 2005 21 of 70 3.2 serial digital input the GS9090 contains a current mode differential serial digital input buffer, allowing the device to be connected to smpte 259m -c compliant serial digital input signals. the input buffer has internal 50 termination resistors, which are connected to ground via the term pin. if the input signa l is ac coupled to the device, the signal source common mode level will be set in ternally to approximately 1.45v. 3.3 clock and data recovery the output of the serial digital input buffer passes to the GS9090's internal reclocker block. the function of this block is to lock to the inpu t data stream, extract a clean clock, and retime the serial digital data to remove high frequency jitter. the operating centre frequency of the inte rnal reclocker is 270mb/s where the input jitter tolerance (ijt) is +/- 0.2ui at this rate. if the reclocker locks to the signal, it will pr ovide internal pll_lock and carrier_detect signals to the lock detect block of the device. 3.3.1 internal vco and phase detector the GS9090 uses an internal vco and pf d as part of the internal reclocker's phase-locked loop. each block requires a +1.8v dc power supply, which is supplied via the vco_vdd / vco_gnd and pll_vdd / pll_gnd pins. 3.4 serial-to-parallel conversion the retimed data and phase-locked clock signals from the internal reclocker are fed to the serial-to-parallel converter. the fu nction of this block is to extract 10-bit parallel data words from the reclocked serial data stream and simultaneously present them to the smpte and dvb-asi word alignment blocks.
GS9090 data sheet 28201 - 1 july 2005 22 of 70 3.5 modes of operation the GS9090 has two basic modes of operation: auto mode and manual mode. auto mode is enabled when the application layer sets the auto/man pin high, and manual mode is enabled when the auto/man pin is set low. as indicated in figure 3-1 , each mode supports both smpte and dvb-asi input signals. in addition, data-through functionality is possible when the GS9090 is in manual mode. figure 3-1: GS9090?s modes of operation 3.5.1 lock detect once the internal recl ocker has locked to the received serial digital data stream, the lock detect block of the GS9090 searches for the appropriate sync words, and indicates via the locked output pin wh en the device has successfully achieved lock. the locked pin is designed to be stab le. it will not toggle during the locking process, nor will it glitch du ring a synchronous switch. lock detection is a continuous process, which begins after a system reset and continues until the device is powered dow n or held in reset. this process is summarized in figure 3-2 . GS9090 manual mode dvb-asi functionality data-through functionality auto mode smpte functionality smpte functionality dvb-asi functionality
GS9090 data sheet 28201 - 1 july 2005 23 of 70 figure 3-2: lock detection process the lock detection algorithm first determines if a valid serial digital input signal has been presented to the device by sampling the internal carrier_detect signal. when the serial data input is considered inva lid the locked pin will be set low, and all device outputs will be forced low, except pclk. the pclk output frequency will be 27mhz +/- 7.5% over the temperature range of -20 o c to +85 o c. if a valid serial digital input signal has been detected, and the device is in auto mode, the lock algorithm will attempt to de tect the presence of either smpte trs words or dvb-asi sync words. assuming that a valid 270mb/s smpte or dvb-asi signal has been app lied to the device, the locked pin will be set high and the synchronous and asynchronous lo ck times will be as listed in the ac electrical characteristics table. in manual mode, the applicatio n layer must set the smpte_bypass and dvb_asi pins appropriately so that the lock detect block will search for either smpte trs or dvb-asi sync words. sync hronous and asynchronous lock times are also listed in the ac electrical characteristics table. power up or reset no yes (device in manual mode) valid serial digital input? internal reclocker locked? device in auto mode? smpte trs or dvb-asi sync words detected? application layer must set smpte_bypass and dvb_asi pins to support different functionalities. sets smpte_bypass and dvb_asi pins low device device sets locked pin low device sets locked pin high device sets smpte_bypass and dvb_asi status pins (section 3.5.2) device outputs accurate 27mhz clock on pclk pin device outputs 27mhz +/- 7.5% clock on pclk pin device sets all other output pins low (input data invalid) yes no no no yes yes
GS9090 data sheet 28201 - 1 july 2005 24 of 70 note: the pclk output will continue to o perate at 27mhz +/- 7.5% during the lock detection process. only when the device is locked (locked = high) will the pclk output an accurate 27mhz signal. for smpte and dvb-asi inputs, the lock detect block will only assert the locked output pin high if (1) the reclocker has locked to the input data stream, and (2) trs or dvb-asi sync words ha ve been correctly identified. for serial inputs that do not conform to smpte or dvb-asi formats, one of the following will occur once th e reclocker has locked: 1. in manual mode, data will be passed dire ctly to the parallel outputs without any further processing taking place and th e locked signal will be asserted high if and only if the smpte_bypass and dvb_asi input pins are set low (see data-through functionality on page 29 ); or 2. in auto mode, the locked signal will be asserted low, the parallel outputs will be set to logic low, and the smpte_bypass and dvb_asi output signals will also be set low. if the internal reclocker does not lock to the inpu t, the internal pll_ lock signal will be low, and the lock detect block will not se arch for sync words. the locked signal will be set low, and all device outputs except pclk will be forced low. the pclk output frequency will be 27mhz +/- 7.5% over the temp erature range of -20 o c to +85 o c. 3.5.2 auto mode recall that the GS9090 is in auto mode when the auto/man input pin is set high by the application layer. in this mode, smpte_bypass and dvb_asi become output status pins. table 3-1 shows the status of these pins when different serial digital video signals are applied. table 3-1: auto mode output status signals pin settings format smpte_bypass dvb_asi sd smpte high low dvb-asi low high not smpte or dvb-asi* low low *note: in this case the device will not be lo cked (locked = low), and all digital output pins except pclk will be set low (see lock detect on page 22 )
GS9090 data sheet 28201 - 1 july 2005 25 of 70 3.5.3 manual mode recall that the GS9090 is in manual mode when the auto/man input pin is set low by the applicatio n layer. in this mode the smpte_bypass and dvb_asi pins become input signals, and the app lication layer determines the operating mode of the device by setting these pins as shown in table 3-2 . 3.6 smpte functionality the GS9090 enters smpte mode once the device has detected smpte trs sync words and locked to the input data stream as described in lock detect on page 22 . the GS9090 will remain in smpte mode until such time that smpte trs sync words fail to be detected. the lock detect block may also drop out of smpte mode under any of the following conditions: ?smpte_bypass is asserted low in manual mode ? reset is asserted low ? locked is low (i.e. the device loses lock to the input signal) trs word detection is a cont inuous process, and the device will identify both 8-bit and 10-bit trs words. in auto mode, the gs9 090 sets the smpte_bypass pin high and the dvb_asi pin low to indicate that it has locked to a smpte input data stream. when operating in manual mode, the application layer must assert the dvb_asi pin low and the smpte_bypass pin high in order to enable smpte operation. table 3-2: manual mode input status signals pin settings format smpte_bypass dvb_asi sd smpte high low dvb-asi x high not smpte or dvb-asi (data-through mode)* low low *note: see data-through functionality on page 29 for more detail on data-through mode
GS9090 data sheet 28201 - 1 july 2005 26 of 70 3.6.1 smpte descrambling and word alignment after serial-to-parallel conversion, the inte rnal 10-bit data bus is fed to the smpte descramble and word alignment internal bloc k. the function of this block is to carry out nrzi-to-nrz decoding, descrambling according to smpte 259m-c, and word alignment of the data to the trs sync words. note: when 8-bit data is embedded in the 10-bit smpte signal, the two lsbs (dout[1:0]) must be set to zero for word alignm ent to work correctly. word alignment occurs when two consecutive valid trs words (sav and eav inclusive) with the same bit alignment have been detected (1 video line). in normal operation, re-syn chronization of the word alignment process will only take place when two consecutive iden tical trs word positions have been detected. when automatic or manual s witch line lock handling occurs (see switch line lock handling on page 27 ), word alignment re-syn chronization will occur on the next received trs code word. the device will drop out of smpte mode, only after 6 consecutive missing trs timing words. 3.6.2 internal flywheel the GS9090 has an internal flywheel for the generation of internal / external timing signals, the detection and correction of certain error condition s, and the automatic detection of video standards. the flywheel is only operational in smpte mode. the flywheel 'learns' the video standard by monitoring the horizontal and vertical reference information contained in the trs id words of the received video stream. full synchronization of the flywheel to the received video standard therefore requires one complete video frame. once synchronization has be en achieved, the fl ywheel will continue to monitor the received trs timing information to maintain synchronization. the fw_en input pin controls the synchr onization mechanism of the flywheel. when this input signal is low, the flywheel will re-synchronize all pixel and line based counters on every received trs id word. when fw_en is held high, re-synchronization of the pixel and line based counters will take place afte r 3 consecutive video lines with identical trs timing are identified. this provides a measure of noise immunity for output timing signal generation. the flywheel will be disabled shou ld the locked signal or reset signal be low. this will occur regardless of the setting of the fw_en pin.
GS9090 data sheet 28201 - 1 july 2005 27 of 70 3.6.3 switch line lock handling the principle of switch line lock handling is that the switching of synchronous video sources will only disturb the horizontal timi ng and alignment of the stream, whereas the vertical timing rema ins in synchronization. to account for the horizontal disturbanc e caused by a synchronous switch, it is necessary to re-synchronize the flywheel immediately after the switch has taken place. rapid re-synchronization of the GS9090 to the new video standard can be achieved by controlling the flywheel using the fw_en pin. at every pclk cycle the device samples the fw_en pin. when the fw_en pin is set low anywhere within the active lin e, the flywheel will re-synchronize immediately to the next trs word. the ability to manua lly re-synchronize the flywh eel is also important when switching asynchronous sources or to implement other non-standardized video switching functions. the GS9090 also implements automatic swit ch line lock handling. by utilizing both the synchronous switch point defined in smpte rp168, and the automatic video standards detect function, the device automa tically re-synchronizes the flywheel at the switch point. this will occur whether or not the device has detected trs word errors. word alignment re-synchronization will also take place at this time. automatic switch line lock handling will oc cur regardless of the setting of the fw_en pin. the switch line is as defined in table 3-3 . table 3-3: switch line positi on for 270mb/s digital systems system video format sampling signal standard parallel interface serial interface switch line number 525 720x483/59.94 (2:1) 4:2:2 125m 125m 259m-c 10, 273 625 720x576/50 (2:1) 4:2:2 bt.656 125m 259m-c 6, 319
GS9090 data sheet 28201 - 1 july 2005 28 of 70 3.6.4 hvf timing signal generation the GS9090 extracts critical timing pa rameters from either the received trs signals (fw_en = low) or from the internal flywheel-timing generator (fw_en = high). horizontal blanking period (h), vertical bl anking period (v), and field odd / even timing (f) are extracted and are available for output on any of the multi-function output port pins, if so programmed (see programmable multi-function outputs on page 56 ). the h signal timing is configurable via the h_config bit of the internal ioproc_disable register as either active line-based blanking, or trs-based blanking (see table 3-14 in error correction and insertion on page 43 ). the default setting of this bit (after reset has been asserted) is low. active line-based blanking is enabled when the h_config bit is set low. in this mode, the h output is high for the entire horizontal blanking period, including the eav and sav trs words. this is the defa ult h timing used by the device. when h_config is se t high, trs based blanking is enabled. in this case, the h output will be high for the entire horizontal blanking period as indicated by the h bit in the received trs id words. the timing of these signals is shown in figure 3-3 . note 1: when the internal fifo is conf igured for video mode, the h, v, and f signals will be timed to the data output fr om the fifo (see video mode on page 46 ). note 2: when the GS9090 is configured for low-latency mode, the h, v, and f output timing will be trs-based only as shown in GS9090 low-latency mode on page 58 . active line-based timing is not availa ble in this mode, and the setting of the h_config host interface bit will be ignored. figure 3-3: h,v,f timing y/cr/cb data out pclk h v f xyz (eav) 000 000 3ff xyz (sav) 000 000 3ff h signal timing: h_config = low (default) h_config = high
GS9090 data sheet 28201 - 1 july 2005 29 of 70 3.7 dvb-asi functionality the GS9090 enters dvb-asi mode once t he device has detected 32 consecutive dvb-asi words without a single word or disparity error being generated. the device will remain in dvb-asi mode un til 32 consecutive dvb-asi words or disparity errors are detected, or until smpte trs id words have been detected. the lock detect block may also drop out of dvb-asi mode under the following conditions: ? reset is asserted low ? both auto/man and dvb_asi are asserted low ? locked pin is low (i.e. the device loses lock to the input signal) k28.5 sync patterns in the received dvb-asi data stream will be detected by the device in either inverted or non-inverted form. in auto mode, the gs90 90 sets the smpte_bypass pin low and the dvb_asi pin high to indicate that it has locked to a dvb-asi input data stream. when operating in manual mode, the applicatio n layer must set the dvb_asi pin high to enable dvb-asi operation. the smpte_bypass pin will be ignored. 3.7.1 dvb-asi 8b/10b decoding after serial-to-parallel conversion, the internal 10-bit data bus is fed to the dvb-asi 8b/10b decode and word alignment block. the function of this block is to word align the data to the k28.5 sync characters, and 8b/10b decode and bit-swap the data to achieve bit alignment with the data outputs. the extracted 8-bit data will be presented to dout [7:0], bypa ssing all internal smpte mode data processing. 3.7.2 status signal outputs in dvb-asi mode, the dout9 and dout 8 pins will be configured as dvb-asi status signals worderr a nd syncout respectively. syncout will be high whenever a k28.5 sy nc character is pr esent on the output. worderr will be high whenever the dev ice has detected an illegal code word or there is a running disparity error. 3.8 data-through functionality the GS9090 may be configured by the application layer to operate as a simple serial-to-parallel converter. in this mode , the device presents data to the output data bus without performing any decoding, descrambling, or word-alignment. data-through functionality is enabled only when the application layer sets the auto/man , smpte_bypass , and dvb_asi input pins low. under these conditions, the lock detect block allows 270mb/s input data not conforming to smpte or dvb-asi streams to be reclocked and deserialized. if the device is in
GS9090 data sheet 28201 - 1 july 2005 30 of 70 data-through mode, and the internal reclocker locks to the data stream, the locked pin will be set high. if the application layer does not set the auto/man pin low, the GS9090 will set the smpte_bypass and dvb_asi signals to logic low if presented with a data stream without smpte trs id words or dvb-asi sync words. in addition, the locked pin and data bus outp ut pins will be forced low. 3.9 additional processing features the GS9090 contains additional processing features that are available in smpte mode only (see smpte functionality on page 25 ). 3.9.1 fifo load pulse to aid in the implementation of auto-pha sing and line synchronization functions, the GS9090 will generate a fifo load pulse to reset line-based fifo storage. this fifo_ld signal is available for output on one of the multi-function output port pins, if so programmed (see programmable multi-function outputs on page 56 ). the fifo_ld pulse will normally be high, but will go low for one pclk period, thereby generating a fifo write reset signal. by default, the fifo load pulse will be generat ed such that it is co-timed to the sav xyz code word presented to the output da ta bus. this co-timing ensures that the next pclk cycle will correspond with the first active sample of the video line. note: when the internal fifo of the gs909 0 is set to operate in video mode, the fifo_ld pulse can be used to drive the rd_reset input to the device (see video mode on page 46 ). figure 3-4 shows the default timing relationship between the fifo_ld signal and the output video data. figure 3-4: fifo_ld pulse timing 3.9.1.1 programmable fifo load position the position of the fifo_ld pulse can be moved in pclk increments from its default position to a maximum of one full line. the offset number of pclk's must be programmed in the fifo_ld_position[12: 0] internal register (address 28h), via the host interface. 000 3ff 000 xyz y'cbcr data pclk fifo_ld
GS9090 data sheet 28201 - 1 july 2005 31 of 70 the fifo_ld_position[12:0] register is designed to accommodate the longest sd line length. if the user programs a value greater than the maximum line length at the operating sd standard, the fifo_ld pulse will not be generated. after a device reset, the fifo _ld_position[12:0] register is set to zero and the fifo_ld pulse will assume the default timing. 3.9.2 ancillary data detection and indication the GS9090 will detect all type s of ancillary data in either the vertical or horizontal data spaces. the anc_detect status signal is provided to indicate the position of ancillary data in the output data stream. this signal is available for output on the multi-function output port pins, if so programmed (see programmable multi-function outputs on page 56 ). the anc_detect status signal is synchr onous with pclk and can be used as a clock enable to external logic, or as a write enable to an external fifo or other memory device. the anc_detect signa l will be asserted high whenever ancillary data is detected in the video data stream (see figure 3-5 ). both 8-bit and 10-bit ancillary data preambles will be detected by the GS9090. note 1: when the internal fifo is c onfigured for video mode, the anc_detect signal will be timed to the data output from the fifo (see video mode on page 46 ). note 2: for performance in low latency mode, see GS9090 low-latency mode on page 58. figure 3-5: anc_detect status signal 3.9.2.1 programmable ancillary data detection although the GS9090 will detect all types of an cillary data by default, it also allows the application layer to specifically program up to five different ancillary data types for detection. this is acco mplished by setting the anc_ type registers via the host interface (see table 3-4 ). for each data type to be detected, the host interface must program the did and/or sdid of the ancillary data type of inte rest. the GS9090 will compare the received did and/or sdid with the programmed valu es and assert anc only if an exact match is found. the same timing shown in figure 3-5 will be used. 3ff 000 3ff did dbn dc anc data anc data csum blank anc_detect y'cbcr data pclk
GS9090 data sheet 28201 - 1 july 2005 32 of 70 if any did or sdid value is set to zero in the anc_type register, no comparison or match will be made for th at value. for example, if the did is programmed but the sdid is set to zero, the device will de tect all ancillary data types matching the did value, regardless of the sdid. if bo th did and sdid values are non-zero, then the received ancillary data type must ma tch both the did and sdid cases before the device will assert anc_detect high. in the case where all five did and sdid values are set to zero, the GS9090 will detect all ancillary data types. this is the default setting after a device reset. where one or more, but less than five, did and/or sdid values have been programmed, then on ly those matching ancillary da ta types will be detected and indicated. note: see smpte 291m for a defini tion of ancillary data terms. table 3-4: host interface description for pr ogrammable ancillary data type registers register name bit name description r/w default anc_type 1 address: 0ah 15-8 anc_type1[15:8] used to program the did for ancillary data detection at anc_detect output r/w 0 7-0 anc_type1[7:0] used to program the sdid for ancillary data detection at anc_detect output. should be set to zero if no sdid is present in the ancillary data packet to be detected. r/w 0 anc_type 2 address: 0bh 15-8 anc_type2[15:8] used to program the did for ancillary data detection at anc_detect output r/w 0 7-0 anc_type2[7:0] used to program the sdid for ancillary data detection at anc_detect output. should be set to zero if no sdid is present in the ancillary data packet to be detected. r/w 0 anc_type 3 address: 0ch 15-8 anc_type3[15:8] used to program the did for ancillary data detection at anc_detect output r/w 0 7-0 anc_type3[7:0] used to program the sdid for ancillary data detection at anc_detect output. should be set to zero if no sdid is present in the ancillary data packet to be detected. r/w 0 anc_type 4 address: 0dh 15-8 anc_type4[15:8] used to program the did for ancillary data detection at anc_detect output r/w 0 7-0 anc_type4[7:0] used to program the sdid for ancillary data detection at anc_detect output. should be set to zero if no sdid is present in the ancillary data packet to be detected. r/w 0 anc_type 5 address: 0eh 15-8 anc_type5[15:8] used to program the did for ancillary data detection at anc_detect output r/w 0 7-0 anc_type5[7:0] used to program the sdid for ancillary data detection at anc_detect output. should be set to zero if no sdid is present in the ancillary data packet to be detected. r/w 0
GS9090 data sheet 28201 - 1 july 2005 33 of 70 3.9.3 edh packet detection the GS9090 will determine if edh packets are present in the incoming video data and assert the edh_detect output status signal appropriately. edh_detect will be set high when edh packets have been detected and will remain high until edh packets are no long er present. the si gnal will be set low at the end of the vertical blanking (falling edge of v) if an edh packet has not been received and detected during vertical blanking. edh_detect is available for output on th e multi-function outpu t port pins, if so programmed (see programmable multi-function outputs on page 56 ). additionally, the edh_detect bit is st ored in the data_format register at address 04h (see table 3-7 ). 3.9.4 edh flag detection as described in edh packet detection on page 33 , the GS9090 can detect edh packets in the received data stream. th e edh flags for ancillary data, active picture, and full field areas are extr acted from the detected edh packets and placed in the edh_flag_in register of the device ( table 3-5 ). when the edh_flag_update bit in the data_format register ( table 3-7 ) is set high by the applicati on layer, the gs90 90 will update the an cillary data, full field, and active picture edh flags acco rding to smpte rp165. the updated edh flags are placed in the edh_flag_out register ( table 3-6 ). the edh packet output from the device w ill contain the updated flags. one set of flags is provided for both fields 1 and 2. field 1 flag data will be overwritten by field 2 flag data. when no edh packets are detected (edh_detect = low), the ues flags in the edh_flag_out register will be set high to signify that the received signal does not support the error detection practice. these flags are set regardless of the setting of the edh_flag_update bit. note: when edh_flag_update is lo w with edh packets in the video stream, the content of the edh_flag_out register is not valid and should be ignored. both edh_flag registers may be read by th e host interface at any time during the received frame except on the lines defined in smpte rp165 where these flags are updated. the GS9090 will also extract the crc valid or ?v? bit for both acti ve picture and full field crcs. the ap_crc_v bit in the data_format register provides the active picture crc valid bit status, and the ff_c rc_v bit provides the full field crc valid bit status (see table 3-7 ). when edh_detect = low, these bits will be cleared. the flag register values remain set until overwritten by the decoded flags in the next received edh packet in the following field. when no edh packet is detected during vertical blanking, the flag registers will be cleared at the end of the vertical blanking period.
GS9090 data sheet 28201 - 1 july 2005 34 of 70 table 3-5: host interface description for edh flag registers register name bit name description r/w default edh_flag_in address: 02h 15 ? not used ? ? 14 anc-ues_in ancillary unknown error status flag r 0 13 anc-ida_in ancillary internal device error detected already flag. r 0 12 anc-idh_in ancillary internal device error detected here flag. r 0 11 anc-eda_in ancillary error detected already flag. r 0 10 anc-edh_in ancillary error detected here flag. r 0 9 ff-ues_in full field unknown error status flag. r 0 8 ff-ida_in full field internal device error detected already flag. r 0 7 ff-idh_in full field internal device error detected here flag. r 0 6 ff-eda_in full field error detected already flag. r 0 5 ff-edh_in full field error detected here flag. r 0 4 ap-ues_in active picture unknown error status flag. r 0 3 ap-ida_in active picture internal device error detected already flag. r0 2 ap-idh_in active picture internal device error detected here flag r 0 1 ap-eda_in active picture error detected already flag. r 0 0 ap-edh_in active picture error detected here flag. r 0
GS9090 data sheet 28201 - 1 july 2005 35 of 70 table 3-6: host interface description for edh flag registers register name bit name description r/w default edh_flag_out address: 03h 15 ? not used ? ? 14 anc-ues ancillary unknown error status flag r 0 13 anc-ida ancillary internal device error detected already flag. r 0 12 anc-idh ancillary internal device error detected here flag. r 0 11 anc-eda ancillary error detected already flag. r 0 10 anc-edh ancillary error detected here flag. r 0 9 ff-ues full field unknown error status flag. r 0 8 ff-ida full field internal device error detected already flag. r 0 7 ff-idh full field internal device error detected here flag. r 0 6 ff-eda full field error detected already flag. r 0 5 ff-edh full field error detected here flag. r 0 4 ap-ues active picture unknown error status flag. r 0 3 ap-ida active picture internal device error detected already flag. r0 2 ap-idh active picture internal device error detected here flag r 0 1 ap-eda active picture error detected already flag. r 0 0 ap-edh active picture error detected here flag. r 0
GS9090 data sheet 28201 - 1 july 2005 36 of 70 3.9.5 smpte 352m payload identifier the GS9090 can receive and detect the presence of the smpte 352m payload identifier ancillary data pa cket. this four word payload identifier packet may be used to indicate the transport mechanism, frame rate and line scanning / sampling structure. upon reception of this packet, the device will extract the four words describing the video format being transported and make this information available to the host interface via the four video_format 8 bit registers ( table 3-8 ). the device will also indicate the version of the payload packet in bit 7 of the data_format register ( table 3-7 ). when this bit is set high the received smpte 352m packet is version 1, otherwise it is version 0. the video_format register s will only be updated if the received checksum is the same as the locally calculated checksum. note: the video_format registers will not be updat ed with 352m payload data if the packets are not on the correct video line (as stated in this standard). these registers will be cl eared to zero, indicating an und efined format, if the device loses lock to the input data stream (l ocked = low), or if the smpte_bypass pin is asserted low. this is also the default setting after a device reset. table 3-7: host interface descri ption for data format register register name bit name description r/w default data_format address: 04h 15-12 ? not used ? ? 11 edh_flag_update when set high by t he application layer, the device will update the ancillary data, full field, and active picture edh flags according to smpte rp165. r/w 0 10 ap_crc_v active picture crc valid bit. r 0 9 ff_crc_v full field crc valid bit. r 0 8 edh_detect set high by the device when edh packets are detected in the incoming video data. r0 7 version_352m indicates whether decoded smpte 352m packet is version 0 or version 1. see smpte 352m payload identifier on page 36 . r0 6-5 ? not used ? ? 4 std_lock standard lock bit. this bit will be set high when the flywheel has achieved full synchronization to the received video standard. see automatic video standard and data format detection on page 37 . r0 3-0 data_format[3:0] displays the data format being carried on the serial digital interface. see video standard indication on page 38 . r0
GS9090 data sheet 28201 - 1 july 2005 37 of 70 3.9.6 automatic video standard and data format detection the GS9090 can independently detect the input video standard and data format by using the timing parameters extracted fr om the received trs id words. total samples per line, active sample s per line, total lines per field/frame, and active lines per field/frame are all calculated and pr esented to the host interface via the raster_structure registers ( table 3-9 ). also associated with the raster_str ucture registers is the status bit, std_lock. the GS9090 will set std_lo ck high when the flywheel has achieved full synchronization to the receiv ed video standard. std_lock is stored in the data_format register ( table 3-7 ). the four raster_structure registers, as well as the std_lock status bit will default to zero after a de vice reset. they will also defa ult to zero if the device loses lock to the input data stream (l ocked = low), or if the smpte_bypass pin is asserted low. table 3-8: host interface description for smpte 352m payload identifier registers register name bit name description r/w default video_format_out_b address: 10h 15-8 smpte 352m byte 4 data will be available in this register when video payload identification packets are detected in the data stream. r0 7-0 smpte 352m byte 3 data will be available in this register when video payload identification packets are detected in the data stream. r0 video_format_out_a address: 0fh 15-8 smpte 352m byte 2 data will be available in this register when video payload identification packets are detected in the data stream. r0 7-0 smpte 352m byte 1 data will be available in this register when video payload identification packets are detected in the data stream. r0 table 3-9: host interface descriptio n for raster structure registers register name bit name description r/w default raster_structure1 address: 11h 15-11 ? not used ? ? 10-0 raster_structure1[10:0] total lines per frame r 0 raster_structure2 address: 12h 15-13 ? not used ? ? 12-0 raster_structure2[12:0] total words per line r 0 raster_structure3 address: 13h 15-13 ? not used ? ? 12-0 raster_structure3[12:0] words per active line r 0 raster_structure4 address: 14h 15-11 ? not used ? ? 10-0 raster_structure4[10:0] active lines per field r 0
GS9090 data sheet 28201 - 1 july 2005 38 of 70 3.9.6.1 video standard indication as well as detecting the video standard, the GS9090 can extract the data format being carried on the serial digital interface (i.e. sdti, sdi, or dvb-asi). this information is represented by bits 0 to 3 of the data_format register ( table 3-7 ), which may be read by the application layer via the host interface. data_format[3:0] regist er codes are shown in table 3-10 . the data_format[3:0] register defaults to fh (undefined) after a system reset. the register will also be set to its default value if the device is not locked (locked = low), or if both smpte_bypass and dvb_asi pins are low. 3.9.7 error detectio n and indication the GS9090 contains a number of error detection functions to enhance operation of the device when operating in smpte mo de. these functions, except lock error detection, will not be ava ilable in dvb-asi mode ( dvb-asi functionality on page 29 ) or data-through mode ( data-through functionality on page 29 ). the device maintains an error status register at address 01h called error_status. each type of error has a spec ific flag or bit in this register that is set high whenever that error is detected ( table 3-11 ). all bits in the error_status register , except the lock_err bit, will be cleared at the start of each video field or when read by the host interface, whichever condition occurs first. table 3-10: data format register codes data format[3:0] data format applicable standards 0h sdti dvcpro - no ecc smpte 321m 1h sdti dvcpro - ecc smpte 321m 2h sdti dvcam smpte 322m 3h sdti cp smpte 326m 4h other sdti fixed block size ? 5h other sdti variable block size ? 6h sdi ? 7h dvb-asi ? 8h ~ eh reserved ? fh unknown data format ?
GS9090 data sheet 28201 - 1 july 2005 39 of 70 all bits, with the exception of the lock_err , will also be cleare d if a change in the video standard is detected, or under the following conditions: ? locked is asserted low ?smpte_bypass is asserted low in manual mode the whole error_status register, incl uding the lock_err bit, will be set low during a system reset (reset = low). in addition to the error_status regi ster, a register called error_mask is included to select the specific error conditions that will be detected ( table 3-12 ). there is one bit in the er ror_mask register fo r each type of error represented in the error_status register. the bits of the error_mask register will de fault to '0' after a device reset, thus allowing all error types to be detected. the host interface may disable individual error detection by setting the corres ponding bit high in this register. error conditions are also indicated to the application layer via the status signal pin data_error . this output pin is an inverted lo gical 'or'ing of each error status flag stored in the error_status register. data_error is normally high, but will be set low by the device when an erro r condition that ha s not been masked is detected. table 3-11: host interface descri ption for error status register register name bit name description r/w default error_status address: 01h 15-7 ? not used ? ? 6 vd_std_err video standard error flag. set high when a mismatch between the received smpte 352m packets (version 1 or version 0) and the calculated video standard occurs. r0 5 ff_crc_err full field crc error flag. set high when a full field (ff) crc mismatch has been detected in field 1 or 2 r0 4 ap_crc_err active picture crc error flag. set high when an active picture (ap) crc mismatch has been detected in field 1 or 2. r0 3 lock_err lock error flag. set high whenever the locked pin is low (indic ating the device is not correctly locked). r0 2 cs_err checksum error flag. set high when ancillary data packet checksum error has been detected. r0 1 sav_err start of active video error flag. set high when trs errors are detected in either 8-bit or 10-bit trs words. r0 0 eav_err end of active video error flag. set high when trs errors are detected in either 8-bit or 10-bit trs words. r0
GS9090 data sheet 28201 - 1 july 2005 40 of 70 3.9.7.1 video standard error detection if a mismatch between the received smpte 352m packets and the calculated video standard occurs, the GS9090 will in dicate a video standar d error by setting the vd_std_err bit of the error_status register high. the device will detect errors in both version 1 and version 0 352m packets. 3.9.7.2 edh crc error detection the GS9090 calculates the full field ( ff) and active picture (ap) crc words according to smpte rp165 in support of error detection and handling packets in sd signals. these calculated crc values are compared with the received crc values. if a mismatch is detected, the error is flagged in the ap_crc_err and/or ff_crc_err bits of the error_status register. these two flags are shared between fields 1 and 2. the ap_crc_err bit will be set high when an active picture crc mismatch has been detected in field 1 or 2. the ff_ crc_err bit will be set high when a full field crc mismatch has been detected in field 1 or 2. edh crc errors will only be indicated when the device has correctly received edh packets. smpte rp165 specifies the calculation ranges and scope of edh data for standard 525 and 625 component digita l interfaces. the GS9090 will utilize these standard ranges by default. table 3-12: host interface description for error mask register register name bit name description r/w default error_mask address: 25h 15-7 ? not used ? ? 6 5 vd_std_err_mask video standard error flag mask bit. r/w 0 ff_crc_err_mask full field crc error flag mask bit. r/w 0 4 ap_crc_err_mask active picture crc error flag mask bit r/w 0 3 lock_err_mask lock error flag mask bit. r/w 0 2 cs_err_mask checksum error flag mask bit. r/w 0 1 sav_err_mask start of active video error flag mask bit. r/w 0 0 eav_err_mask end of active video error flag mask bit. r/w 0
GS9090 data sheet 28201 - 1 july 2005 41 of 70 if the received video format does not correspond to 525 or 625 digital component video standards as determined by the flywheel pixel and line counters, then one of two schemes for determining the edh calculation ranges will be employed: 1. ranges will be based on the line and pixel ranges programmed by the host interface; or 2. in the absence of us er-programmed ca lculation ranges, ranges will be determined from the received trs timing information. the registers available to the host interface for programming edh calculation ranges include active picture and full field line/pixel start and end positions for both fields. table 3-13 shows the relevant registers, wh ich default to '0' after a device reset. if any or all of these register values are zero, then the edh crc calculation ranges will be determined from the flywheel generated timing. the first active and full field pixel will always be the first pixel after the sav trs code word. the last active and full field pixel will always be the last pixe l before the start of the eav trs code words. table 3-13: host interface description for edh calculatio n range registers register name bit name description r/w default ap_line_start_f0 address: 15h 15-11 ? not used ? ? 10-0 ap_line_start_f0[10:0] field 0 active picture start line data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ap_line_end_f0 address: 16h 15-11 ? not used ? ? 10-0 ap_line_end_f0[10:0] field 0 active picture end line data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ap_line_start_f1 address: 17h 15-11 ? not used ? ? 10-0 ap_line_start_f1[10:0] field 1 active picture start line data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ap_line_end_f1 address: 18h 15-11 ? not used ? ? 10-0 ap_line_end_f1[10:0] field 1 active picture end line data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ff_line_start_f0 address: 19h 15-11 ? not used ? ? 10-0 ff_line_start_f0[10:0] field 0 full field start line data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ff_line_end_f0 address: 1ah 15-11 ? not used ? ? 10-0 ff_line_end_f0[10:0] field 0 full field end line data used to set edh calculation range outside of smpte rp 165 values. r/w 0
GS9090 data sheet 28201 - 1 july 2005 42 of 70 ff_line_start_f1 address: 1bh 15-11 ? not used ? ? 10-0 ff_line_start_f1[10:0] field 1 full field start line data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ff_line_end_f1 address: 1ch 15-11 ? not used ? ? 10-0 ff_line_end_f1[10:0] field 1 full field end line data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ap_pixel_start_f0 address: 1dh 15-13 ? not used ? ? 12-0 ap_pixel_start_f0[12:0] field 0 active picture start pixel data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ap_pixel_end_f0 address: 1eh 15-13 ? not used ? ? 12-0 ap_pixel_end_f0[12:0] field 0 active picture end pixel data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ap_pixel_start_f1 address: 1fh 15-13 ? not used ? ? 12-0 ap_pixel_start_f1[12:0] field 1 active picture start pixel data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ap_pixel_end_f1 address: 20h 15-13 ? not used ? ? 12-0 ap_pixel_end_f1[12:0] field 1 active picture end pixel data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ff_pixel_start_f0 address: 21h 15-13 ? not used ? ? 12-0 ff_pixel_start_f0[12:0] field 0 full field start pixel data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ff_pixel_end_f0 address: 22h 15-13 ? not used ? ? 12-0 ff_pixel_end_f0[12:0] field 0 full field end pixel data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ff_pixel_start_f1 address: 23h 15-13 ? not used ? ? 12-0 ff_pixel_start_f1[12:0] field 1 full field start pixel data used to set edh calculation range outside of smpte rp 165 values. r/w 0 ff_pixel_end_f1 address: 24h 15-13 ? not used ? ? 12-0 ff_pixel_end_f1[12:0] field 1 full field end pixel data used to set edh calculation range outside of smpte rp 165 values. r/w 0 table 3-13: host interface description for ed h calculation range re gisters (continued) register name bit name description r/w default
GS9090 data sheet 28201 - 1 july 2005 43 of 70 3.9.7.3 lock error detection the locked pin of the GS9090 indicates th e lock status of the internal reclocker and lock detect blocks of the device. only when the locked pin is asserted high has the device correctl y locked to the received data stream (see lock detect on page 22 ). the GS9090 will also indicate lock error to the host interface when locked = low by setting the lock_err bit in the error_status register high. 3.9.7.4 ancillary data checksum error detection the GS9090 will calculate checksums for all received ancillary data and compare the calculated values to the received ch ecksum words. if a mismatch is detected, the cs_err bit of the error_status register will be set high. although the GS9090 will calc ulate and compare checksum values for all ancillary data types by default, the host interfac e may program the device to check only certain types of ancillary data chec ksums. this is accomplished via the anc_type registers as described in programmable ancillary data detection on page 31 . 3.9.7.5 trs error detection trs error flags are generated by the GS9090 when: 1. the received trs h timing does not co rrespond to the internal flywheel timing; or 2. the received trs hamming codes are incorrect. both 8-bit and 10-bit sav and eav trs wo rds are checked for timing and data integrity errors. these are flagged via the sav_err an d/or eav_err bits of the error_status register. note: h timing based trs errors will only be generated if the fw_en pin is set high. f & v timing errors ar e not detected or corrected. 3.9.8 error correction and insertion in addition to signal error detection and indication, the GS9090 may also correct certain types of errors by inserting correc ted code words, checksums, and trs values into the data stream. these featur es are only available in smpte mode and the ioproc_en pin must be set high by the application layer. individual correction features may be enabled or di sabled by setting bits 0 to 3 in the ioproc_disable register ( table 3-14 ). all of the ioproc_disable re gister bits default to '0' after a device reset, enabling all of the processing features. to disable any individual error correction feature, the host interface must set the corresponding bit high in the ioproc_disable register.
GS9090 data sheet 28201 - 1 july 2005 44 of 70 3.9.8.1 illegal code remapping if the illegal_remap bit of the iopr oc_disable register is set low, the GS9090 will remap all codes within the active picture between t he values 3fch and 3ffh to 3fbh. all codes within the active picture area between the values 00h and 03h will be re-mapped to 04h. in addition, 8-bit trs and ancillary data preambles will be remapped to 10-bit values if this feature is enabled. table 3-14: host interface description fo r internal processing disable register register name bit name description r/w default ioproc_disable address: 00h 15-10 ? not used ? ? 9 anc_pkt_ext ancillary packet ex traction. when the fifo is configured for ancillary data extraction mode, the application layer must set this bit high to begin extraction. note: setting anc_pkt_ext low will not automatically disable ancill ary data extraction (see ancillary data extraction and reading on page 51 ). r/w 0 8-7 fifo_mode[1:0] fifo mode: these bits control which mode the internal fifo is operating in (see table 3-15 ) r/w 0 6 h_config horizontal sync timing output configuration. set low for active line blanking timi ng. set high for h blanking based on the h bit setting of the trs word. see figure 3-3 in hvf timing signal generation on page 28. r/w 0 5-4 not used. 3 illegal_remap illegal code re-map ping. correction of illegal code words within the active pict ure. set high to disable. the ioproc_en pin must be set high. r/w 0 2 edh_crc_ins error detection & handling (edh) cyclical redundancy check (crc) error correction insertion. set high to disable. the ioproc_en pin must be set high. r/w 0 1 anc_csum_ins ancillary data checksum insertion. set high to disable. the ioproc_en pin must be set high. r/w 0 0 trs_ins timing reference signal insertion. the device will correct trs based errors when set low (see trs error correction on page 45 ). the ioproc_en pin must also be high. set this bit high to disable. r/w 0
GS9090 data sheet 28201 - 1 july 2005 45 of 70 3.9.8.2 edh crc error correction if the edh_crc_ins bit of the ioproc_disable re gister is set low, the GS9090 will generate and in sert active picture and fu ll field crc words into the edh data packets rece ived by the device. additionally, when edh_crc_ins is low, the device will set the active picture and full field crc ?v? bits high in the edh packet (see edh flag detection on page 33 ). the ap_crc_v and ff_crc_v regi ster bits will only report the received edh validity flags. edh crc calculation ranges are described in edh crc error detection on page 40 . note: although the GS9090 will modify and insert edh crc words and edh packet checksums, the device will only update edh error flags when the edh_flag_update bit is set high (see edh flag detection on page 33 ). 3.9.8.3 ancillary data checksum error correction when ancillary data checksum error correc tion and insertion is enabled, the GS9090 will generate and in sert ancillary data checksums for all ancillary data words by default. where user specified ancillary data has b een programmed into the anc_type registers of the host interface (see programmable ancillary data detection on page 31 ), only the checksums for th e ancillary data programmed will be corrected. this feature is enabled when the anc_csum_ins bi t of the ioproc_disable register is set low. 3.9.8.4 trs error correction when trs error correction and insertion is enabled, the GS9090 will generate and insert 10-bit trs code words as required. trs word generation will be performed in accord ance with the timing parameters generated by the flywheel to provide an element of noise immunity. as a result, trs correction will only take place if the flywheel in enabled (fw_en = high). in addition, the trs_ins bit of the io proc_disable register must be set low. note: only h timing based er rors will be corrected (see trs error detection on page 43 ).
GS9090 data sheet 28201 - 1 july 2005 46 of 70 3.10 internal fifo operation the GS9090 contains an internal video line-based fifo, which can be programmed by the application layer to work in any of the following modes: 1. video mode, 2. dvb-asi mode, 3. ancillary data extraction mode, or 4. bypass mode the fifo can be configured to one of t he four modes by using the host interface to set the fifo_mode[1:0] bits of the ioproc_disable register (see table 3-14 in error correction and insertion on page 43 ). the setting of these bits is shown in table 3-15 . to enable the fifo, the application layer must also set the fifo_en pin high. additionally, if th e fifo is configured for video mode or ancillary data extraction mode, the ioproc_en pin must be set high. the fifo is fully asynchronous, allowing simultaneous read and write access. it has a depth of 2048 words, which will accommodate 1 full line of sd video for both 525 and 625 standards. the fifo is 15 bi ts wide: 10 bits for video data and 5 bits for other signals, such as h, v, f, edh_detect, and anc_detect. 3.10.1 video mode the internal fifo is in video mode wh en the application layer sets the fifo_en and ioproc_en pins high, and the fifo_mode[1:0] bits in the ioproc_disable register are conf igured to 00b. by default, the fifo_mode[1:0] bits are set to 00b by the device whenev er the smpte_bypass pin is set high and the dvb_asi pin is set low (i.e. the device is in smpte mode); however, the application layer may program the fifo_mode[1:0] bits as required. figure 3-6 shows the input and output signals of the fifo when it is configured for video mode. table 3-15: fifo configuration bit settings fifo mode fifo_mode[1:0] register setting fifo_en pin setting ioproc_en pin setting video mode 00b high high dvb-asi mode 01b high x ancillary data extraction mode 10b high high bypass mode 11b x x note: ?x? signifies ?don?t care?. the pin is ignored and may be set high or low.
GS9090 data sheet 28201 - 1 july 2005 47 of 70 figure 3-6: fifo in video mode when operating in video mode, the gs90 90 will write data sequentially into the fifo, starting with the first active pixel in location zero of the memory. in this mode, it is possible to use the fifo for clock phase interchange and data alignment / delay. the extracted h, v, and f information will also be written into the fifo. the h, v, and f outputs will be timed to the video data read from the fifo by the application interface (see hvf timing signal generation on page 28 ). the device will ensure write-side synchroniz ation is maintained, according to the extracted pclk and flywheel timing information. full read-control of the fifo is made availabl e to the application interface such that data will be clocked out of the fifo on the rising edge of the externally provided rd_clk signal. when there is a high -to-low transition at the rd_reset pin the first pixel presented to the video data bus will be the first 000 of the sav (see figure 3-7 ). the fifo_ld pulse may be used to control the rd_reset pin. note: the rd_reset pulse should not be held low for more than one rd_clk cycle. figure 3-7: rd_reset pulse timing in video mode, the anc_dete ct output signal will be timed to the data output from the fifo (see ancillary data de tection and indi cation on page 31 for more detail). wr_clk (pclk) h fifo (video mode) rd_clk application interface 10-bit video data 10-bit video data v f h v f anc anc wr_reset rd_reset internal edh_detect edh_detect 000 3ff 000 xyz y'cbcr data rd_clk rd_reset
GS9090 data sheet 28201 - 1 july 2005 48 of 70 3.10.2 dvb-asi mode the internal fifo is in dvb-asi mode when the application layer sets the fifo_en pin high, and the fifo_mode[ 1:0] bits in the ioproc_disable register are configured to 01b. by default, the fifo_mode[1:0] bits are set to 01b by the device whenever the dvb_asi pin is set high (i.e. the device is in dvb-asi mode); however, the application layer may program the fifo_mode[1:0] bits as required. figure 3-8 shows the input and output signals of the fifo when it is configured for dvb-asi mode. figure 3-8: fifo in dvb-asi mode when operating in dvb-asi mode, the GS9090's fifo can be used for clock rate interchange operat ion. the extracted 8-bit mpeg packets will be written into the fifo at 27mhz based on the syncout sign al from the internal dvb-asi decoder block. the syncout and worderr bits are also stored in the fifo (see status signal outputs on page 29 ). when syncout goes high, k28.5 stuffi ng characters have been detected and no data will be written into the fifo. data is read out of the fifo by the ap plication layer using the rd_clk pin. in dvb-asi mode, the rd_reset pin is not used. 3.10.2.1 reading from the fifo the fifo contains internal read and write pointers used to designate which spot in the fifo the mpeg packet will be read from or written to. these internal pointers control the status flags fifo_empty an d fifo_full, which are available for output on the multi-f unction output port pins, if so programmed (see programmable multi-function outputs on page 56 ). in the case where the write pointer is or iginally ahead of the read pointer, the fifo_empty flag will be set hi gh when both pointers ar rive at the same address (see block a in figure 3-11 ). the application layer can use this flag to determine when to stop reading from the device. wr_clk (pclk gated with syncout) syncout worderr fifo (dvb-asi mode) rd_clk 8-bit mpeg data 8-bit mpeg data worderr syncout fifo_full fifo_empty internal application interface
GS9090 data sheet 28201 - 1 july 2005 49 of 70 a write and read pointer offset may be programmed in the fifo_empty_offset[9:0] register of the host interface. if an offset value is programmed in this register, the fifo_empty flag will be set high when the read and write pointers of the fifo are at th e same address, and will remain high until the write pointer reaches the programmed offset. once the pointer offset has been exceeded, the fifo_empty flag will go low (see block b in figure 3-11 ). in the case where the read pointer is originally ahead of the write pointer, the fifo_full flag will be set high when both pointers arrive at the same address (see block c in figure 3-11 ). the application layer can use this flag to determine when to begin reading from the device. a read and write pointer offset may also be programmed in the fifo_full_offset[9:0] register of the hos t interface. if an offset value is programmed in th is register, the fifo_full flag will be set high when the read and write pointers of the fifo are at th e same address, and will remain set high until the read pointer reaches the programmed offset. once the pointer offset has been exceeded, the fifo_full fl ag will be cleared (see block d in figure 3-11 ). gating the rd_clk using the fifo_empty flag using the asynchronous fifo_empty fl ag to gate rd_clk requires external clock gating circuity to gene rate a clean burst clock (see figure 3-9 ). an example circuit for this application is shown in figure 3-10 . figure 3-9: burst clock figure 3-10: example circuit to gate rd_clk using the fifo_empty flag fifo_empty q q set cl r d q q set cl r d q q set cl r d rd_clk gated rd_clk fifo_empty gated rd_clk rd_clk
GS9090 data sheet 28201 - 1 july 2005 50 of 70 figure 3-11: reading from the fifo in dvb-asi mode fifo_empty address read pointer exmple 2: fifo empty flag operation when fifo_empty[9:0] = 3ffh write pointer fifo 1023 2047 0 fifo_empty read pointer write pointer exmple 1: fifo empty flag operation when fifo_empty[9:0] = 0h 0 2047 fifo address fifo 2047 5 read pointer address write pointer fifo_full fifo exmple 3: fifo full flag operation when fifo_full[9:0] = 0h fifo_full write pointer read pointer exmple 4: fifo full flag operation when fifo_full[9:0] = 3ffh 2047 1023 0 address a c b d
GS9090 data sheet 28201 - 1 july 2005 51 of 70 3.10.3 ancillary data extraction mode the internal fifo is ancilla ry data extraction mode when the application layer sets the fifo_en and ioproc_en pins high, and the fifo_mode[1:0] bits in the ioproc_disable register are configured to 10b. once the fifo enters ancillary data extraction mode, it takes 2200 pclks (82us) to initialize the fifo before ancillary data extraction can begin. in this mode, the fifo is divided into tw o separate blocks of 1024 words each. this allows ancillary data to be written to one side of the fifo while the application layer reads from the other. thus, in each ha lf of the fifo, th e GS9090 will write the contents of the packets up to a maximum of 1024 8-bit words. as described in programmable ancillary data detection on page 31 , up to five specific types of ancillary data to be extracted can be programmed in the anc_type registers. if the anc_type regist ers are all set to zero, the device will extract all types of ancillary data. the entire packet, including the ancillary data flag (adf), data identification (did), secondary data identification (sdid), data count (dc) , and checksum word will be written into the memory. the device will dete ct ancillary data packet did's placed anywhere in the video data stream, including the active picture area. additionally, the lines from which the packets are to be extracted from can be programmed into the anc_line_a[10:0] and anc_line_b[10:0] registers, allowing ancillary data from a maximum of two lines per fr ame to be extracted. if only one line number register is programm ed (with the other set to zero), ancillary data packets will be extracte d from one line per frame only. when both registers are set to zero, the device will extract packets from all lines. the application layer reads th e extracted ancillary data through the ho st interface starting at address 02ch up to 42bh inclusive (1024 words). this must be done while there is a valid video signal present at the serial input and the device is locked (locked = high). 3.10.3.1 ancillary data extraction and reading to start ancillary data ex traction, the anc_pkt_ext bit of the ioproc_disable register must be set high (see table 3-14 in error correction and insertion on page 43 ). packet extraction will begin in the fo llowing frame after this bit has been set high. note: ancillary data extraction will not be gin until 2200 pclk s (82us) after the device has entered in to ancillary data extraction mode (fifo_mode[1:0] = 10b), regardless of the setting of the anc_pkt_ext bit. when the fifo is confi gured for ancillary data extr action mode, setting the ioproc_en pin low will disable packet ex traction. if ioproc_en is low, the setting of the anc_pkt_ext host interface bit will be ignored.
GS9090 data sheet 28201 - 1 july 2005 52 of 70 clearing the anc_pkt_ext bit will not au tomatically disable ancillary data extraction. to disable ancillary data extracti on, switch th e fifo into bypass mode by setting fifo_mode[1:0] = 11b. 2200 pclk cycles after the device re-enters ancillary data extraction mode, data extraction will commence immediately if anc_pkt_ext is still high. the application layer can use the anc_de tect output flag available on the i/o output pin (see programmable multi-function outputs on page 56 ) to determine the length of the ancillary data extracted and when to begin reading the extracted data from memory. recall that anc_detect is high whenever ancillary data has been detected. in addition, the data count (dc) word, which is located th ree words after the ancillary data flag (adf) in the memory, can be read to determine how many valid user data words (udw) are present in the extracted packet (see smpte 291m for more details). the dc value can then be used to preset how many address reads must be performed to obtain only the user data words. ancillary data will be written in to the first half of the fifo until it is full or until the anc_data_switch bit is toggled (i .e. a high-to-low or low-to-high transition). if the anc_data_switch bit is not toggled, extracted data will not be written into memory after the first half of the fifo is full (see block a in figure 3-12 ). when the anc_data_switch bit is toggl ed, new extracted data will be written to the second half starting at address zero (see block b in figure 3-12 ). the data in the first half of the fifo may still be read. once the data in the first half of the fifo has been read, the anc_data_switch may be toggled again to enable the second half of the fifo to be read. the first half of the fifo will be clea red, and the device will conti nue to write ancillary data to the second half of the fifo (see block c in figure 3-12 ). if the anc_data_switch bit is toggled again, new extracte d data will be written to the first half starting at address zero (see block d in figure 3-12 ). the data in the second half of the fi fo may still be read. toggling anc_data_switch again will cl ear the second half of the fifo and restore the read and write pointers to the situation shown in block a. the switching process (shown in blocks a to d in figure 3-12 ) will continue with each toggle of the anc_data_switch bit. note: at least 1100 pclk cycles (41us) must pass between toggles of the anc_data_switch bit. the anc_data_switch bit must be toggled at a point in the video where no extraction is occu rring (i.e. the anc_detect signal is low).
GS9090 data sheet 28201 - 1 july 2005 53 of 70 figure 3-12: ancillary data extraction and reading %% anc_data_switch = high anc_data_switch bit is toggled high. new ancillary data is written to second half of fifo starting at adress zero. application layer continues to read from the first half of the fifo. application layer read pointer internal write pointer 0 1023 1023 0 application layer read pointer internal write pointer 0 0 1023 1023 anc_data_switch = low 0 1023 internal write pointer application layer read pointer anc_data_switch = high 0 1023 anc_data_switch bit is toggled high. new ancillary data is written to first half of fifo starting at address zero. application layer continues to read from second half of fifo. toggling anc_data_switch back low will clear the second half of the fifo and go back the situation depicted in box a. application layer read pointer internal write pointer %% 0 anc_data_switch = low 1023 0 1023 anc_data_switch toggled low. first half of fifo cleared and ancillary data read from second half of fifo. device continues to write ancillary data to second half of fifo. a b c d anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data anc_data note: at least 1100 pclk cycles must pass between toggles of the anc_data_switch bit. the bit must be toggled at a point where no extraction is occuring (i.e. the anc signal is low).
GS9090 data sheet 28201 - 1 july 2005 54 of 70 3.10.3.2 clearing the anc data fifo when switching to anc fifo mode from any other mode and on power up, the user must follow one of the 2 methods be low to ensure that the fifo is fully cleared. clearing anc fifo method 1: 1. enable anc fifo mode (write 10b into the fifo_mode register). 2. wait for anc_fifo_ready bit to be asserted. 3. toggle (low-to-high-to-low) an c_data_switch bit (bit 12 of io_config register) twice. clearing anc fifo method 2: 1. power on device. 2. set fifo_en pin high. 3. enable anc fifo mode (write 10b into the fifo_mode register). 4. set fifo_en pin low. 5. set fifo_en pin high. 3.10.4 bypass mode the internal fifo is in bypass mode when the application layer sets the fifo_en or ioproc_en pin low, or the fifo_m ode[1:0] bits in the ioproc_disable register are configured to 11b. by default, the fifo_mode[1:0] bits are set to 11b by the device whenever both the smpte_bypass and dvb_asi pins are low; however, the application layer may program the fifo_mode[1:0] bits as required. in bypass mode, the fifo is not inserted into the video path and data is presented to the output of the devic e synchronously with the pclk output. the fifo will be disabled and placed in static mode to save power.
GS9090 data sheet 28201 - 1 july 2005 55 of 70 3.11 parallel data outputs data outputs are valid on the rising edge of pclk as shown in figure 3-13 . figure 3-13: pclk to data & co ntrol signal output timing the data is presented in 10-bit format and may be scrambled or unscrambled, framed or unframed. the output data format is defined by the settings of the external smpte_bypass and dvb_asi pins (see table 3-16 ). recall that in manual mode, these pins are set by the application layer as inputs to the device. in auto mode, however, the GS9090 sets these pins as output status signals. 3.11.1 parallel data bus the parallel data outputs of the GS9090 su pport both lvttl and lvcmos levels. these outputs use either +1.8v or +3.3 v, supplied at the io_vdd and io_gnd pins. when interfacing with +5v logic le vels, the io_vdd pins should be supplied with +3.3v. for a low power connection, the io_vdd pins may be connected to +1.8v. all outputs, including the pclk output, will be driven to a high-i mpedance state if the reset signal is asserted low with the exception of the stat pins and the data_error pin which will maintain the last st ate they were in for the duration that reset is asserted. 50% t oh t od v oh v ol v oh v ol v oh v ol v oh v ol control signal output dout[9:0] pclk table 3-16: parallel data output format pin settings output data format dout[9:0] smpte_bypass dvb_asi 10-bit data data low low 10-bit multiplexed sd luma / chroma high low 10-bit dvb-asi dvb-asi data low high
GS9090 data sheet 28201 - 1 july 2005 56 of 70 3.11.2 parallel output in smpte mode when the device is operating in smpte mode (see smpte functionality on page 25 ), sd data is presented to the output bus in multiplexed format. the data will be output on the dout[9:0 ] pins and word aligned according to trs id words. 3.11.3 parallel output in dvb-asi mode when operating in dvb-asi mode (see dvb-asi functionality on page 29 ), the extracted 8-bit data words will be presen ted on dout[7:0] such that dout7 = hout is the most significant bit of th e decoded transport stream data and dout0 = aout is the least significant bit. in addition, dout9 and dout8 will be conf igured as the dvb-asi status signals worderr and syncout respectively. see status signal outputs on page 29 for a description of these dvb- asi specific output signals. 3.11.4 parallel output in data-through mode when operating in data-through mode (see data-through functionality on page 29 ), the GS9090 presents data to the ou tput data bus without performing any decoding, descrambling, or word-alignment. as described in data-through functionality on page 29 , the data bus outputs will be forced to logic low if the device is set to operate in auto mode but cannot identify smpte trs id or dvb-asi syn c words in the input data stream. 3.12 programmable multi-function outputs the GS9090 has a multi-function output port that uses 4 pins, stat0 through stat3. each pin can be programmed via the host interface to output one of the following signals: h, v, f, fifo_ld , anc_detect, edh_detect, fifo_full, and fifo_empty. table 3-17: output signals available on multi-function output ports output status signal reference h hvf timing signal generation on page 28 v hvf timing signal generation on page 28 f hvf timing signal generation on page 28 fifo_ld fifo load pulse on page 30 anc_detect ancillary data detection and indication on page 31 edh_detect edh packet detection on page 33 fifo_full reading from the fifo on page 48 fifo_empty reading from the fifo on page 48
GS9090 data sheet 28201 - 1 july 2005 57 of 70 the registers that determine the signals present on the stat [3:0] pins are labelled stat0_config[2:0], stat1_config[ 2:0], stat2_config[2:0], and stat3_config[2:0] respectively. table 3-18 shows the setting of the io_config registers for each of the available output signals. the default setting for each io_config r egister depends on the configuration of the device and the internal fifo mode selected. this is shown in table 3-19 . note: signals not relevant to the partic ular mode of operation will be ignored and be high-impedance when programmed to be displayed on the stat[3:0] pins. for example, the fifo_full an d fifo_empty flags can only be displayed on the stat[3:0] pins when the device is in dvb-asi mode. if the fifo_full or fifo_empty value (110 and 111 respectively) is programmed into the io_config registers when the device is in smpte mode, the value will be ignored and the i/o pin will be se t to a high impedance state. table 3-18: io_config settings function i/o io_config setting h output 000b v output 001b f output 010b fifo_ld output 011b anc_detect output 100b edh_detect output 101b fifo_full output 110b fifo_empty output 111b table 3-19: stat [3:0] output default configuration device configuration io_config register i/o function default io_config setting smpte functionality smpte_bypass = high dvb_asi = low fifo: video mode or ancillary data extraction mode stat0_config output h 000b stat1_config output v 001b stat2_config output f 010b stat3_config output fifo_ld 011b dvb-asi dvb_asi = high fifo: dvb-asi mode stat0_config output fifo_full 110b stat1_config output fifo_empty 111b stat2_config output high z 000b stat3_config output high z 000b
GS9090 data sheet 28201 - 1 july 2005 58 of 70 3.13 GS9090 low-latency mode when the ioproc_en pin is set low, the GS9090 will enter a low-latency mode such that the parallel data will be output with the mini mum pclk latency possible. the fifo and all processing blocks except the descrambling and word alignment blocks will be bypassed when smpte_bypass is high. low-latency mode will also be selected when smpte_bypass is set low, regardless of the setting of the ioproc_en signal (see table 3-20 ). in dvb-asi mode, the device will have a higher latency than low-latency mode, although this latency will be less than smpte mode. note: when in low-latency mode, the stat pin output of the anc packet flag is delayed by 15 pclk cycles with respect to the parallel video output. the length of the flag matches the le ngth of the anc packet. when the GS9090 is configured for low-late ncy mode, the h, v, and f output timing will be trs based blanking only as shown in figure 3-14 . active line-based timing is not available and the setting of the h_ config host interface bit will be ignored. data-through smpte_bypass = low dvb_asi = low stat0_config output high z 000b stat1_config output high z 000b stat2_config output high z 000b stat3_config output high z 000b table 3-19: stat [3:0] output default configuration (continued) device configuration io_config register i/o function default io_config setting table 3-20: pin settings in low-latency mode ioproc_en setting smpte_bypass setting latency (pclk cycles) low low 9 high low 10 low high 10 high high 25 note: latency applies to parallel processing core only.
GS9090 data sheet 28201 - 1 july 2005 59 of 70 figure 3-14: h,v,f timing in low-latency mode 3.14 gspi host interface the gspi, or gennum serial peripheral interface, is a 4-wire interface provided to allow the host to enable additional features of the GS9090 and/or to provide additional status information through configuration registers in the device. the gspi comprises a serial data inpu t signal sdin, serial data output signal sdout, an active low chip select cs , and a burst clock sclk. because these pins are shared with the jtag interface port, an additional control signal pin jtag/host is provided. when jtag/host is low, the gspi interface is enabled. when operating in gspi mode, the sclk, sdin, and cs signals are provided by the application interface. the sdout pi n is a non-clocked loop-through of sdin and may be connected to the sdin of anot her device, allowing mu ltiple devices to be connected to the gspi chain. the interface is illustrated in figure 3-15 . figure 3-15: gspi application interface connection all read or write access to the GS9090 is initiated and terminated by the host processor. each access always begins with a 16-bit command word on sdin indicating the address of the register of interest. this is followed by a 16-bit data word on sdin in write mode, or a 16-bit data word on sdout in read mode. y/cr/cb data out pclk h v f xyz (eav) 000 000 3ff xyz (sav) 000 000 3ff application host sclk sclk sclk cs1 sdout sdin sdout sdout cs sdin sdin cs2 GS9090 GS9090 cs
GS9090 data sheet 28201 - 1 july 2005 60 of 70 3.14.1 command word description the command word consists of a 16-bit word transmitted msb first and contains a read/write bit, an auto-increment bit and a 12-bit address. figure 3-16 shows the command word format and bit configurations. command words are clocked into the GS9090 on the rising edge of the serial clock sclk, which operates in a burst fashion. when the auto-increment bit is set lo w, each command word must be followed by only one data word to ensure proper operation. if the auto-increment bit is set high, the following data word will be wri tten into the address specified in the command word, and subseq uent data words will be wri tten into incremental addresses from the previous data word. this facilitates multiple address writes without sending a command word for each data word. auto-increment may be used for both read and write access. 3.14.2 data read and write timing read and write mode timing for the gspi interface is shown in figure 3-18 and figure 3-19 respectively. the timing parameters are defined in table 3-21 . when several devices are connected to the gspi chain, only one cs must be asserted during a read sequence. during the write sequence, all command and following data words input at the sdin pin are output at th e sdout pin as is. where several devices are connected to the gspi chain, data can be written simultaneously to all the devices that have cs set low. table 3-21: gspi timing parameters parameter definition specification t 0 the minimum duration of time chip select, cs , must be low before the first sclk rising edge. 1.5 ns t 1 the minimum sclk period. 18.5 ns t 2 duty cycle tolerated by sclk. 40% to 60% t 3 minimum input setup time. 1.5 ns t 4 write cycle: the minimum duration of time between the last sclk command (or data word if the auto-increment bit is high) and the first sclk of the data word. 37.1 ns t 5 read cycle: the minimum duration of time between the last sclk command (or data word if the auto-increment bit is high) and the first sclk of the data word. 148.4 ns t 5 read cycle - fifo in anc extraction mode: the minimum duration of time between the last sclk command (or data word if the auto-increment bit is high) and the first sclk of the data word. 222.6 ns t 6 minimum output hold time. 1.5 ns
GS9090 data sheet 28201 - 1 july 2005 61 of 70 figure 3-16: command word format figure 3-17: data word format figure 3-18: gspi read mode timing figure 3-19: gspi write mode timing t 7 the minimum duration of time between the last sclk of the gspi transaction and when cs can be set high. 37.1 ns t 8 minimum input hold time. 1.5 ns table 3-21: gspi timing parameters (continued) parameter definition specification msb lsb a4 a5 a6 a8 a7 a9 a3 a2 a1 a0 a10 a11 autoinc rsv rsv r/w rsv = reserved. must be set to zero. r/w: read command when r/w = 1 write command when r/w = 0 msb lsb d4 d5 d6 d8 d7 d9 d3 d2 d1 d0 d10 d11 d12 d13 d14 d15 sclk cs sdin sdout t 5 t 6 r/w rsv rsv autoinc a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 r/w rsv rsv autoinc a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 t 3 sclk cs sdin sdout t 0 t 1 t 2 t 4 r/w rsv rsv autoinc a11 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a10 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 r/w rsv rsv autoinc a11 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a10 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 t 7 t 8
GS9090 data sheet 28201 - 1 july 2005 62 of 70 3.14.3 configuration and status registers table 3-22 summarizes the GS9090's internal st atus and configuration registers. all of these registers are available to the host via the gspi and are all individually addressable. where status registers contain less than the full 16 bits of information, two or more registers may be combined at a single logical address. table 3-22: GS9090 internal registers address register name reference 00h ioproc_disable error correction and insertion on page 43 01h error_status error detection and indication on page 38 02h edh_flag_in edh flag detection on page 33 03h edh_flag_out edh flag detection on page 33 04h data_format video standard indication on page 38 05h io_config programmable multi-function outputs on page 56 06h fifo_empty_offset reading from the fifo on page 48 07h fifo_full_offset reading from the fifo on page 48 08h - 0eh anc_type ancillary data detection and indication on page 31 11h - 14h raster_structure automatic video standard and data format detection on page 37 15h - 24h edh_calc_ranges edh crc error detection on page 40 25h error_mask error detection and indication on page 38 28h fifo_ld_position programmable fifo load position on page 30 02ch - 42bh internal fifo ancillary data extraction mode on page 51
GS9090 data sheet 28201 - 1 july 2005 63 of 70 3.15 reset operation when the reset signal on the GS9090 is de-asserted (reset = low to high) the locked and data[9:0] signals are valid after a period of 200ns after fhe rising edge of the reset signal. (see figure 3-20 ) the application layer should not sample the locked or data[9:0] signals during this time. figure 3-20: reset timing 3.16 jtag operation when the jtag/host pin is set high by the application layer, the host interface port (as described in gspi host interface on page 59 ) will be configured for jtag test operation. in this mode, pins 16, 17, 19, and 20 become tms, tck, tdo, and tdi respectively. in addition, the reset pin will operate as the test reset pin, as well as resetting the internal registers. boundary scan testing using the jtag interface will be possib le in this mode. there are two methods in which jtag can be used on the GS9090: 1. as a stand-alone jtag interface to be used at in-circuit ate (automatic test equipment) during pcb assembly; or 2. under control of the host for applicat ions such as system power self tests. when the jtag tests are applied by ate, care must be taken to disable any other devices driving the digital i/o pins. if the te sts are to be applied only at ate, this can be accomplished with tri-state bu ffers used in conjunction with the jtag/host input signal. this is shown in figure 3-21 . alternatively, if the test ca pabilities are to be used in the system, the host may still control the jtag/host input signal, but some means for tri-stating the host must exist in order to use the interface at ate. this is represented in figure 3-22 . dout[9:0] locked reset 200ns invalid data
GS9090 data sheet 28201 - 1 july 2005 64 of 70 figure 3-21: in-circuit jtag figure 3-22: system jtag 3.17 device power up the GS9090 has a recommended power supply sequence. to ensure correct power up, power the core_vdd pins before the io_vdd pins. in order to initialize all internal operating conditions to their default state the application layer must hold the reset pin low for a minimum of t reset = 1ms. (see figure 3-23 ) device pins can be driven prior to power up without causing damage. figure 3-23: reset pulse application host GS9090 cs_tms sclk_tck sdin_tdi sdout_tdo jtag_en in-circuit ate p robe application host GS9090 cs_tms sclk_tck sdin_tdi sdout_tdo jtag_en in-circuit ate probe tri-state core_vdd reset t reset +1.71v +1.8v reset reset t reset
GS9090 data sheet 28201 - 1 july 2005 65 of 70 4. references & relevant standards smpte 125m component video signal 4:2:2 ? bit parallel interface smpte 259m 10-bit 4:2:2 component and 4f sc composite digital signals - serial digital interface smpte 291m ancillary data packet and space formatting smpte 293m 720 x 483 active line at 59.94 hz progressive scan production ? digital representation smpte 305.2m serial data transport interface smpte 352m video payload identification for digital television interfaces smpte rp165 error detection checkwords and st atus flags for use in bit-serial digital interfaces for television smpte rp168 definition of vertical interval switching point for synchronous video switching
GS9090 data sheet 28201 - 1 july 2005 66 of 70 5. application information 5.1 typical application circuit (part a) note: for up-to-date component values an d detailed operation of the equalizer, please see the gs9074a data sheet. gs9074a sdi cd sdi vee_d mute vcc_d agc bypass mcladj vee_a note: all resistors in ohms, capacitors in farads, and inductors in henrys, unless otherwise noted. vee_a agc vcc_a sdo sdo vee_d 10n 1 10n cd mute eq_vcc bypass mcladj 470n 6.2n 75 sdi 1u 75 1u 37r4 eq_vcc 4 5 6 2 3 8 7 16 12 13 11 14 15 9 10 470n sdo sdo eq_gnd eq_gnd eq_gnd eq_gnd eq_gnd eq_gnd eq_gnd
GS9090 data sheet 28201 - 1 july 2005 67 of 70 5.2 typical application circuit (part b) locked data_errorb resetb dout9 dout7 dout5 dout3 dout4 dout2 dout6 dout0 dout1 dout8 dvb_asi smpte_bypassb auto_manb fw_en fifo_en ioproc_en jtag_hostb lf- 1 pll_gnd 2 pll_vdd 3 buff_vdd 4 ddi 5 ddi 6 buff_gnd 7 term 8 nc 9 vbg 10 nc 11 ioproc_en 12 jtag/host 13 reset 14 core_vdd 15 cs_tms 16 sclk_tck 17 core_gnd 18 sdout_tdo 19 sdin_tdi 20 io_vdd 21 data_error 22 stat0 23 io_gnd 24 stat1 25 stat2 26 stat3 27 io_gnd 28 io_gnd 42 dout9 41 dout8 40 dout7 39 dout6 38 dout5 37 dout4 36 dout3 35 dout2 34 dout1 33 dout0 32 rd_reset 31 rd_clk 30 io_vdd 29 lf+ 56 vco_gnd 55 lb_cont 54 vco_vdd 53 fifo_en 52 fw_en 51 auto/man 50 smpte_bypass 49 core_gnd 48 dvb_asi 47 locked 46 core_vdd 45 pclk 44 io_vdd 43 1u 10n 1u 1u 100k 0 1u 10n np (0) 10n 1u stat3 10n GS9090 100n 10n (np) 4n7 100k (np) 1u 100k (np) np (np) 100k (np) 10n (np) 10n 10n (np) 0 (np) 0 10n 1u (np) eq_gnd +1.8v gnd_d gnd_d +1.8v gnd_d gnd_d eq_gnd gnd_d gnd_d gnd_a gnd_a gnd_a +1.8v gnd_d eq_gnd io_vdd io_vdd gnd_d io_vdd eq_vcc gnd_d gnd_a gnd_a +1.8v _a io_vdd stat2 stat1 stat0 data[9..0] pclk sclk_tck sdin_tdi csb_tms sdout_tdo rd_resetb rd_clk d di d dib fifo_en fw_en auto_manb ioproc_en resetb jtag_hostb smpte_bypas sb dvb_asi locked data_errorb 1u gnd_a gnd_a +1.8v_a +1.8v_a 1u
GS9090 data sheet 28201 - 1 july 2005 68 of 70 6. package & ordering information 6.1 package dimensions 8.00 pin 1 area a b 2x 0.15 c 6.76 +/- 0.10 3.38 8.00 2x 0.15 c 0.50 0.40 +/- 0.05 6.76 +/- 0.10 6.76 +/- 0.10 3.38 0.23-0.02 +0.03 56x 0.10 m 0.05 ca b mc 0.08 c all dimensions in mm 56x c 0.10 seating plane 0.90 +/- 0.10 0.02-0.02 +0.03 0.20 ref c datum a or b terminal tip detail b 0.50/2 0.50 center d etail b pa d
GS9090 data sheet 28201 - 1 july 2005 69 of 70 6.2 recommended pcb footprint the center pad of the pcb footprint s hould be connected to the core_gnd plane by a minimum of 25 vias. note: suggested dimensions only. final dimensions should conform to customer design rules and process optimizations. 6.3 packaging data 6.4 ordering information note: all dimensions are in millimeters. 7.70 7.70 6.76 6.76 0.50 0.25 0.55 center pad parameter value package type 8mm x 8mm 56-pin qfn package drawing reference jedec m0220 moisture sensitivity level 3 junction to case thermal resistance, j-c 12.2c/w junction to air thermal resistance, j-a (at zero airflow) 25.8c/w psi 9.1c/w pb-free and rohs compliant yes part number package temperature range GS9090-cne3 56-pin qfn 0 o c to 70 o c
caution electrostatic sensitive devices do not open packages or handle except at a static-free workstation gennum corporation mailing address: p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 shipping address: 970 fraser drive, burlington, ontario, canada l7l 5p5 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 gennum japan corporation shinjuku green tower building 27f, 6-14-1, nish i shinjuku, shinjuku-ku, tokyo, 160-0023 japan tel. +81 (03) 3349-5501, fax. +81 (03) 3349-5505 gennum uk limited 25 long garden walk, farnham, surrey, england gu9 7hx tel. +44 (0)1252 747 000 fax +44 (0)1252 726 523 gennum corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. the sale of the circuit or device described herein does not imply any patent license, and gennum makes no representation that the circuit or device is free from patent infringement. gennum and the g logo are registered trademarks of gennum corporation. ? copyright 2003 gennum corporation. all rights reserved. printed in canada. www.gennum.com GS9090 data sheet 28201 - 1 july 2005 70 70 of 70 document identification data sheet the product is in production. gen num reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible. 7. revision history version ecr date changes and/or modifications a 130109 august 2003 new document. b 133382 april 2004 reflected recent design changes in section 3. updated electrical characteristics tables. expanded section on edh flags. transferred document to new template. c 133757 june 2004 modified section 3.16. added new reflow profiles. 0 135948 march 2005 converted to preliminary data sheet. updated pinout diagram to show center pad. updated pin descriptions to add center pad. added reset operation section. updated package dimensions to provide clarity on center pad. added packaging data section. added recommended pcb footprint section. updated absolute maximum ratings table. added application information section with ty pical applicat ion circuits. 1 136665 july 2005 converted to data sheet. updated input swing minimum value in ac elec trical characteristics and added figure 2-1 to clarify meaning. updated gspi sclk to show as a burst clock rather than a continuous one. corrected the units for input termination resistance in the dc electrical characteristics table. updated esd notes in absolute maximum ratings table. updated operational temperature range in dc electrical characteristics table. corrected minor typing errors.

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